KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 5

• Manufacturer Part Number: KSZ8862-16_10
• Description: 2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
• Manufacturer: MICREL [Micrel Semiconductor]

Bus Interface Unit (BIU)................................................................................................................................................33
Queue Management Unit (QMU) ..................................................................................................................................38
Advanced Switch Functions ........................................................................................................................................41
CPU Interface I/O Registers .........................................................................................................................................48
Register Map: Switch and MAC/PHY...........................................................................................................................57
Micrel, Inc.
August 2010
Inter Packet Gap (IPG) ............................................................................................................................................................ 32
Back-Off Algorithm................................................................................................................................................................... 32
Late Collision ........................................................................................................................................................................... 32
Legal Packet Size .................................................................................................................................................................... 32
Flow Control............................................................................................................................................................................. 32
Half-Duplex Backpressure ....................................................................................................................................................... 32
Broadcast Storm Protection ..................................................................................................................................................... 33
Clock Generator....................................................................................................................................................................... 33
Asynchronous Interface ........................................................................................................................................................... 35
Synchronous Interface ............................................................................................................................................................. 36
Summary.................................................................................................................................................................................. 36
BIU Implementation Principles ................................................................................................................................................. 37
Transmit Queue (TXQ) Frame Format..................................................................................................................................... 38
Receive Queue (RXQ) Frame Format ..................................................................................................................................... 39
Spanning Tree Support............................................................................................................................................................ 41
IGMP Support .......................................................................................................................................................................... 42
IPv6 MLD Snooping ................................................................................................................................................................. 42
Port Mirroring Support.............................................................................................................................................................. 42
IEEE 802.1Q VLAN Support .................................................................................................................................................... 43
QoS Priority Support ................................................................................................................................................................ 43
Port-Based Priority................................................................................................................................................................... 43
802.1p-Based Priority .............................................................................................................................................................. 43
DiffServ-Based Priority............................................................................................................................................................. 44
Rate Limiting Support .............................................................................................................................................................. 44
MAC Filtering Function ............................................................................................................................................................ 45
Configuration Interface............................................................................................................................................................. 45
EEPROM Interface .................................................................................................................................................................. 45
Loopback Support.................................................................................................................................................................... 46
I/O Registers ............................................................................................................................................................................ 48
Internal I/O Space Mapping ..................................................................................................................................................... 49
Bit Type Definition.................................................................................................................................................................... 57
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)............................................................................. 57
Bank 0 Base Address Register (0x00): BAR............................................................................................................................ 57
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ........................................................ 57
Bank 0 Bus Error Status Register (0x06): BESR ..................................................................................................................... 58
Bank 0 Bus Burst Length Register (0x08): BBLR..................................................................................................................... 58
Bank 1 Reserved ..................................................................................................................................................................... 58
Bank 2 Host MAC Address Register Low (0x00): MARL ......................................................................................................... 58
Bank 2 Host MAC Address Register Middle (0x02): MARM..................................................................................................... 59
Bank 2 Host MAC Address Register High (0x04): MARH ........................................................................................................ 59
Bank 3 On-Chip Bus Control Register (0x00): OBCR .............................................................................................................. 59
Bank 3 EEPROM Control Register (0x02): EEPCR ................................................................................................................. 60
Bank 3 Memory BIST INFO Register (0x04): MBIR ................................................................................................................. 60
“IGMP” Snooping................................................................................................................................................................... 42
“Multicast Address Insertion” in the Static MAC Table........................................................................................................... 42
Far-end Loopback ............................................................................................................................................................... 46
Near-end (Remote) Loopback............................................................................................................................................. 46
5
KSZ8862-16/32MQL
M9999-081310-3.1