KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 38

• Manufacturer Part Number: KSZ8862-16_10
• Description: 2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
• Manufacturer: MICREL [Micrel Semiconductor]

Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 4KB of memory for back-to-back, non-blocking frame transfer performance. It provides a group of control
registers for system control, frame status registers for current packet transmit/receive status, and interrupts to inform the
host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 3. The first word contains the control information
for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data
follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending on whether
hardware CRC checksum generation is enabled.
Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory,
thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR
register.
Micrel, Inc.
August 2010
Since multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the
status of the packet that is currently being transferred on the MAC interface (which may or may not be the last
queued packet in the TX queue).
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must
be word aligned. Each control word corresponds to one TX packet. Table 4 gives the transmit control word bit
fields.
Bit
15
14-10
9-8
7-6
5-0
Description
TXIC Transmit Interrupt on Completion
When bit is set, the KSZ8862M sets the transmit interrupt after the present frame has been
transmitted.
Reserved
TXDPN Transmit Destination Port Number
When bit is set, this field indicates the destination port(s) where the packet is forwarded
from host system. Set bit 8 to indicate that port 1 is the destination port. Set bit 9 to
indicate that port 2 is the destination port.
Setting all ports to 1 causes the switch engine to broadcast the packet to both ports.
Setting all bits to 0 has no effect. The internal switch engine forwards the packets
according to the switching algorithm in its MAC lookup table.
Reserved
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status
information in the transmit status register TXSR[5:0].
Packet Memory
Address Offset
0
2
4 - up
Table 4. Transmit Control Word Bit Fields
Table 3. Transmit Queue Frame Format
Bit 15
2
Control Word
Byte Count
(maximum size is 1916)
Packet Data
nd
Byte
38
1
st
Bit 0
Byte
KSZ8862-16/32MQL
M9999-081310-3.1