KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 23

• Manufacturer Part Number: KSZ8862-16_10
• Description: 2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
• Manufacturer: MICREL [Micrel Semiconductor]

Functional Description
The KSZ8862M contains two 10/100 physical layer transceivers (PHYs), two MAC units, and a DMA channel integrated
with a Layer-2 switch.
The KSZ8862M contains a bus interface unit (BIU), which controls the KSZ8862M via an 8, 16, or 32-bit host interface.
Physical signal transmission and reception are enhanced through the use of analog circuits in the PHY that make the
design more efficient and allow for low power consumption.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function (port 2 only) performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-
NRZI conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an
external1% 3.01KΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function (port 2 only) performs adaptive equalization, DC restoration, MLT3-to-NRZI
conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to- parallel
conversion.
The receiving side begins with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based upon
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
100BASE-FX Operation
100BASE-FX operation is supported on port 1 and similar to 100BASE-TX operation with the differences being that the
scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-
negotiation is bypassed and auto MDI/MDI-X is disabled.
100BASE-FX Signal Detection
In 100BASE-FX operation, FXSD1 (fiber signal detect), input pin 44, is usually connected to the fiber transceiver
SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater than 1V. When FXSD1
is between 1V and 1.8V, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD1 is over 2.2V, the
fiber signal is detected. Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1
input pin is tied high to force 100BASE-FX mode.
Micrel, Inc.
August 2010
23
KSZ8862-16/32MQL
M9999-081310-3.1