KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 69

• Manufacturer Part Number: KSZ8862-16_10
• Description: 2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
• Manufacturer: MICREL [Micrel Semiconductor]

Bank 32 Switch ID and Enable Register (0x00): SIDER
This register contains the switch ID and the switch enable control.
Bank 32 Switch Global Control Register 1 (0x02): SGCR1
This register contains the global control for the switch function.
Micrel, Inc.
August 2010
Bit
15-8
7-4
3-1
0
Bit
15
14
13
12
11
10
9
8
7-4
3
2-1
0
0
0
0
1
1
0
1
0
0
-
0x0
-
0
Default
0x88
0x8
0x1
Default
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R/W
RW
RW
R/W
RO
RO
RO
RW
Description
Family ID
Chip family ID
Chip ID
0x8 is assigned to KSZ8862M
Revision ID
Start Switch
1 = start the chip.
0 = switch is disabled.
Description
Pass All Frames
1 = switch all packets including bad ones. Used solely for debugging purposes. Works in
conjunction with Sniffer mode only.
Reserved
IEEE 802.3x Transmit Direction Flow Control Enable
1 = enables transmit direction flow control feature.
0 = will not enable transmit direction flow control feature. The switch will not generate any flow
control packets.
IEEE 802.3x Receive Direction Flow Control Enable
1 = enables receive direction flow control feature.
0 = will not enable receive direction flow control feature. The switch will not react to any received
flow control packets.
Frame Length Field Check
1 = checks frame length field in the IEEE packets. If the actual length does not match, the packet
will be dropped (for Length/Type field < 1500).
Aging Enable
1 = enable age function in the chip.
0 = disable age function in the chip.
Fast Age Enable
1 = turn on fast age (800us).
Aggressive Back-Off Enable
1 = enable more aggressive back off algorithm in half-duplex mode to enhance performance. This
is not an IEEE standard.
Reserved
Pass Flow Control Packet
1 = switch will not filter 802.1x “flow control” packets.
Reserved
Link Change Age
1 = link change from “link” to “no link” will cause fast aging (<800us) to age address table faster.
After an age cycle is complete, the age logic will return to normal (300 + 75 seconds).
Note: If any port is unplugged, all addresses will be automatically aged out.
69
KSZ8862-16/32MQL
M9999-081310-3.1