ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 93

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Table 91. LCD Configuration X SFR (LCDCONX, Address 0x9C)
Bit
7
6
[5:0]
Table 92. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5]
0
1
Table 93. LCD Configuration Y SFR (LCDCONY, Address 0xB1)
Bit
7
6
[5:4]
[3:2]
1
0
Table 94. LCD Clock SFR (LCDCLK, Address 0x96)
Bit
[7:6]
[5:4]
[3:0]
Mnemonic
AUTOSCREENSCROLL
INV_LVL
Reserved
SCREEN_SEL
UPDATEOVER
REFRESH
Mnemonic
BLKMOD
BLKFREQ
FD
Mnemonic
Reserved
EXTRES
BIASLVL
V
Default
0
0
0
Default
0
0
0
V
V
A
REF
REF
(V)
×
×
⎛
⎜
⎝
BIASLVL
1
+
BIASLVL
31
Default
0
0
00
0
0
0
Description
Blink mode clock source configuration bits.
BLKMOD
00
01
10
11
Blink rate configuration bits. These bits control the LCD blink rate if BLKMOD (Bits[7:6]) = 11.
BLKFREQ
00
01
10
11
LCD frame rate selection bits (see Table 95 and Table 96).
Description
Reserved.
External resistor ladder selection bit.
EXTRES
0
1
Bias level selection bits (see Table 92).
[ ]
4:0
31
[ ]
4:0
⎞
⎟
⎠
V
V
V
Description
When set, the four screens scroll automatically. The scrolling item is selected by
the BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96). If both BLINKEN in
the LCD configuration SFR (LCDCON, Address 0x95) and AUTOSCREENSCROLL are
set, this bit preempts the blinking mode.
Frame inversion mode enable bit. If this bit is set, frames are inverted every other
frame. If this bit is cleared, frames are not inverted.
These bits should be kept cleared to 0 for proper operation.
These bits select the screen that is being output on the LCD pins. Values of 0, 1, 2,
and 3 select Screen 0, Screen 1, Screen 2, and Screen 3, respectively.
Update finished flag bit. This bit is updated by the LCD driver. When set, this bit
indicates that the LCD memory has been updated and a new frame has begun.
Refresh LCD data memory bit. This bit should be set by the user. When set, the
LCD driver does not use the data in the LCD data registers to update the display.
The LCD data registers can be updated by the 8052. When cleared, the LCD driver
uses the data in the LCD data registers to update display at the next frame.
Result
The blink rate is controlled by software; the display is off
The blink rate is controlled by software; the display is on
The blink rate is 2 Hz
The blink rate is set by BLKFREQ[1:0]
Result (Blink Rate)
1 Hz
1/2 Hz
1/3 Hz
1/4 Hz
Result
External resistor ladder is disabled. Charge pump is enabled
External resistor ladder is enabled. Charge pump is disabled
B
B
Rev. 0 | Page 93 of 148
B
= V
= V
A
A
1/2 Bias
V
V
V
C
C
C
= 2 × V
= 2 × V
A
A
V
V
V
B
B
B
= 2 × V
= 2 × V
ADE5166/ADE5169
A
A
1/3 Bias
V
V
V
C
C
C
= 3 × V
= 3 × V
A
A