ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 28

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE5166/ADE5169 can be configured to generate a PSM
interrupt when the source of V
indicating battery switchover. Setting the EBSO bit in the power
management interrupt enable SFR (IPSME, Address 0xEC) enables
this event to generate a PSM interrupt (see Table 20).
The ADE5166/ADE5169 can also be configured to generate an
interrupt when the source of V
indicating that the V
the EPSR bit in the power management interrupt enable SFR
(IPSME, Address 0xEC) enables this event to generate a PSM
interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing a 0 to these bits. Bit 6 in the peripheral config-
uration SFR (PERIPH, Address 0xF4), VSWSOURCE, tracks
the source of V
V
V
The ADE5166/ADE5169 can be configured to generate a PSM
interrupt when V
urable threshold. This threshold is set in the temperature and
supply delta SFR (DIFFPROG, Address 0xF3), which is described
in Table 50. See the External Voltage Measurement section for
more information. Setting the EVADC bit in the power manage-
ment interrupt enable SFR (IPSME, Address 0xEC) enables this
event to generate a PSM interrupt.
DD
DCIN
and cleared when V
ADC PSM Interrupt
IPSME ADDR. 0xEC
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
SWOUT
DCIN
EVDCIN
FVDCIN
EVADC
FVADC
ESAG
EBSO
FSAG
FBSO
EPSR
FPSR
EBAT
FBAT
. The bit is set when V
DD
changes magnitude by more than a config-
power supply has been restored. Setting
SWOUT
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
EPSR
FPSR
is connected to V
PS2
SWOUT
SWOUT
changes from V
changes from V
RESERVED
SWOUT
FPSM
PTI
Figure 31. Power Supply Management Interrupt Sources
BAT
is connected to
.
DD
BAT
ESAG
FSAG
to V
ES2
to V
FPSM
EPSM
BAT
Rev. 0 | Page 28 of 148
DD
,
,
RESERVED
RESERVED
PSI
The V
measurements take place in the background at intervals to check
the change in V
the start ADC measurement SFR (ADCGO, Address 0xD8), as
described in Table 51. The FVADC flag indicates when a V
measurement is ready. See the External Voltage Measurement
section for details on how V
V
The V
measurements take place in the background at intervals to check
the change in V
lower than the threshold set in the battery detection threshold
SFR (BATVTH, Address 0xFA), described in Table 52; or when a
new measurement is ready in the battery ADC value SFR
(BATADC, Address 0xDF), described in Table 54. See the
Battery Measurement section for more information. Setting the
EBAT bit in the power management interrupt enable SFR (IPSME,
Address 0xEC) enables this event to generate a PSM interrupt.
V
The V
bit in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set when the V
Setting the EVDCIN bit in the IPSME SFR enables this event to
generate a PSM interrupt. This event, which is associated with
the SAG monitoring, can be used to detect that a power supply
(V
initiating a switch from V
BAT
DCIN
DD
) is compromised and to trigger further actions prior to
Monitor PSM Interrupt
EVADC
FVADC
Monitor PSM Interrupt
EADE
TRUE?
DCIN
BAT
DCIN
voltage is measured using a dedicated ADC. These
voltage is measured using a dedicated ADC. These
voltage is monitored by a comparator. The FVDCIN
DCIN
BAT
PENDING PSM
. Conversions can also be initiated by writing to
. The FBAT bit is set when the battery level is
INTERRUPT
EBAT
FBAT
ETI
DD
to V
DCIN
DCIN
EBSO
FBSO
EPSM
BAT
is measured.
.
input level is lower than 1.2 V.
EVDCIN
FVDCIN
ESI
DCIN