ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 62

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Line Cycle Reactive Energy Accumulation Mode
In line cycle reactive energy accumulation mode, the energy
accumulation of the ADE5169 can be synchronized to the
voltage channel zero crossing so that reactive energy can be
accumulated over an integral number of half-line cycles. The
advantages of this mode are similar to those described in the
Line Cycle Active Energy Accumulation Mode section.
In line cycle active energy accumulation mode, the ADE5169
accumulates the reactive power signal in the LVARHR register
(Address 0x06) for an integral number of line cycles, as shown in
Figure 70. The number of half-line cycles is specified in the
LINCYC register (Address 0x12). The ADE5169 can accumulate
active power for up to 65,535 half-line cycles.
Because the reactive power is integrated on an integral number
of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3
SFR (MIRQSTH, Address 0xDE) is set at the end of an active
energy accumulation line cycle. If the CYCEND enable bit (Bit 2)
FROM VOLTAGE
CHANNEL ADC
OUTPUT
FROM
LPF2
VAROS[15:0]
LPF1
VARGAIN[11:0]
ZERO-CROSSING
DETECTION
Figure 70. Line Cycle Reactive Energy Accumulation Mode
DIGITAL-TO-FREQUENCY
VARDIV[7:0]
CONVERTER
%
TO
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CALIBRATION
LINCYC[15:0]
CONTROL
+
+
in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the CYCEND status bit is cleared (see the Energy
Measurement Interrupts section). Another calibration cycle starts
as soon as the CYCEND flag is set. If the LVARHR register
(Address 0x06) is not read before a new CYCEND flag is set, the
LVARHR register is overwritten by a new value.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVARHR register is reset, and a new accu-
mulation starts at the next zero crossing. The number of half-
line cycles is then counted internally until the value programmed
in LINCYC is reached. This implementation provides a valid
measurement at the first CYCEND interrupt after writing to the
LINCYC register. The line reactive energy accumulation uses
the same signal path as the reactive energy accumulation. The
LSB size of these two registers is equivalent.
48
23
LVARHR[23:0]
0
ACCUMULATE REACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LVARHR REGISTER
AT THE END OF LINCYC
HALF-LINE CYCLES
0