ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 90

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within
a reasonable amount of time if the ADE5166/ADE5169 enter an
erroneous state, possibly due to a programming error or electrical
noise. The watchdog is enabled by default with a timeout of two
seconds and creates a system reset if not cleared within two
seconds. The watchdog function can be disabled by clearing the
watchdog enable bit (WDE, Bit 1) in the watchdog timer SFR
(WDCON, Address 0xC0).
The watchdog circuit generates a system reset or interrupt
(WDS, Bit 2) if the user program fails to set the WDE bit within
a predetermined amount of time (set by the PRE bits, Bits[7:4]).
The watchdog timer is clocked from the 32.768 kHz external
crystal connected between the XTAL1 and XTAL2 pins.
Table 87. Watchdog Timer SFR (WDCON, Address 0xC0)
Bit
[7:4]
3
2
1
0
Address
0xC7 to 0xC4
0xC3
0xC2
0xC1
0xC0
Mnemonic
PRE
WDIR
WDS
WDE
WDWR
Default
7
0
0
1
0
Description
Watchdog prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input
clock (32.768 kHz). The PRE bits set which of the upper bits of the counter are used as the
watchdog output, as follows:
PRE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010 to 1111
Watchdog interrupt response bit. When cleared, the watchdog generates a system reset
when the watchdog timeout period has expired. When set, the watchdog generates an
interrupt when the watchdog timeout period has expired.
Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. It is
cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear
WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware
reset from the RESET pin.
Watchdog enable bit. When set, this bit enables the watchdog and clears its counter. The
watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is
not cleared within its selected timeout period, it generates a system reset or watchdog
interrupt, depending on the WDIR bit.
Watchdog write enable bit (see the Writing to the Watchdog Timer SFR (WDCON, Address
0xC0) section).
t
WATCHDOG
Rev. 0 | Page 90 of 148
=
2
PRE
×
XTAL1
2
The WDCON SFR can be written to only by user software if the
double write sequence described in Table 87 is initiated on every
write access to the WDCON SFR.
To prevent any code from inadvertently disabling the watchdog,
a watchdog protection can be activated. This watchdog protection
locks in the watchdog enable and event settings so they cannot
be changed by user code. The protection is activated by clearing
a watchdog protection bit in the flash memory. The watchdog
protection bit is the most significant bit at Address 0x3FFA of
the flash memory. When this bit is cleared, the WDIR bit (Bit 3) is
forced to 0, and the WDE bit is forced to 1. Note that the sequence
for configuring the flash protection bits must be followed to
modify the watchdog protection bit at Address 0x3FFA (see the
Protecting the Flash section).
9
Result (Watchdog Timeout)
15.6 ms
31.2 ms
62.5 ms
125 ms
250 ms
500 ms
1 sec
2 sec
0 sec, automatic reset
0 sec, serial download reset
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