ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 92

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
LCD DRIVER
Using shared pins, the LCD module is capable of directly driving
an LCD panel of 17 × 4 segments without compromising any
ADE5166/ADE5169 functions. It is capable of driving LCDs with
2×, 3×, and 4× multiplexing. The LCD waveform voltages gener-
ated through internal charge pump circuitry support up to 5 V
LCDs. An external resistor ladder for LCD waveform voltage
generation is also supported.
Each ADE5166/ADE5169 has an embedded LCD control circuit,
driver, and power supply circuit. The LCD module is functional
in all operating modes (see the Operating Modes section) and
can store up to four different screens in memory for scrolling
purposes.
Table 89. LCD Driver SFRs
SFR Address
0x95
0x96
0x97
0x9C
0xAC
0xAE
0xB1
0xED
Table 90. LCD Configuration SFR (LCDCON, Address 0x95)
Bit
7
6
5
4
3
2
[1:0]
Mnemonic
LCDEN
LCDRST
BLINKEN
LCDPSM2
CLKSEL
BIAS
LMUX
R/W
R/W
Default
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mnemonic
LCDCON
LCDCLK
LCDSEGE
LCDCONX
LCDPTR
LCDDAT
LCDCONY
LCDSEGE2
Description
LCD enable. If this bit is set, the LCD driver is enabled.
LCD data registers reset. If this bit is set, the LCD data registers are reset to 0.
Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by
BLKMOD (Bits[7:6]) and BLKFREQ (Bits[5:4]) in the LCD clock SFR (LCDCLK, Address 0x96).
Forces LCD off when in PSM2 (sleep) mode. Note that the internal voltage reference must be enabled by
setting the REF_BAT_EN bit in the peripheral configuration SFR (PERIPH, Address 0xF4) to allow LCD
operation in PSM2.
LCDPSM2
0
1
LCD clock selection.
CLKSEL
0
1
Bias mode.
BIAS
0
1
LCD multiplex level.
LMUX
00
01
10
11
Description
LCD configuration (see Table 90).
LCD clock (see Table 94).
LCD segment enable (see Table 97).
LCD Configuration X (see Table 91).
LCD pointer (see Table 98).
LCD data (see Table 99).
LCD Configuration Y (see Table 93).
LCD Segment Enable 2 (see Table 100).
Result
The LCD is disabled or enabled in PSM2 by the LCDEN bit
The LCD is disabled in PSM2 regardless of LCDEN setting
Result
f
f
Result
1/2
1/3
Result
Reserved
2× multiplexing; FP27/COM3 is used as FP27, and FP28/COM2 is used as FP28
3× multiplexing; FP27/COM3 is used as FP27, and FP28/COM2 is used as COM2
4× multiplexing; FP27/COM3 is used as COM3, and FP28/COM2 is used as COM2
LCDCLK
LCDCLK
= 2048 Hz
= 128 Hz
Rev. 0 | Page 92 of 148
LCD REGISTERS
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD configuration SFR (LCDCON,
Address 0x95), LCD Configuration X SFR (LCDCONX,
Address 0x9C), and LCD Configuration Y SFR (LCDCONY,
Address 0xB1) contain general LCD driver configuration infor-
mation including the LCD enable and reset, as well as the method
of LCD voltage generation and multiplex level. The LCD clock
SFR (LCDCLK, Address 0x96) configures timing settings for LCD
frame rate and blink rate. LCD pins are configured for LCD
functionality in the LCD segment enable SFR (LCDSEGE,
Address 0x97) and the LCD Segment Enable 2 SFR (LCDSEGE2,
Address 0xED).