ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 131

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

SERIAL PERIPHERAL INTERFACE (SPI)
The ADE5166/ADE5169 integrate a complete hardware serial
peripheral interface on-chip. The SPI is full duplex so that eight
bits of data are synchronously transmitted and simultaneously
received. This SPI implementation is double buffered, allowing
users to read the last byte of received data while a new byte is
shifted in. The next byte to be transmitted can be loaded while
the current byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO/ZX),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS
SPI REGISTERS
Table 150. SPI SFR List
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Table 151. SPI/I
Bit
[7:0]
Table 152. SPI/I
Bit
[7:0]
Mnemonic
SPI2CTx
Mnemonic
SPI2CRx
2
2
C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
C Receive Buffer SFR (SPI2CRx, Address 0x9B)
Mnemonic
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPISTAT
Default
0
Default
0
R/W
W
R
R/W
R/W
R/W
Description
SPI or I
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I
SPI or I
transferred to the SPI2CRx SFR. A new data byte from the SPI or I
Description
2
2
C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is
8
8
Length (Bits)
8
8
8
Rev. 0 | Page 131 of 148
Default
0
0
0x10
0
0
(P0.7/ SS /T1/RxD2) pins, while the firmware interface is via the
SPI Configuration SFR 1 (SPIMOD1, Address 0xE8), the SPI
Configuration SFR 2 (SPIMOD2, Address 0xE9), the SPI
interrupt status SFR (SPISTAT, Address 0xEA), the SPI/I
transmit buffer SFR (SPI2CTx, Address 0x9A), and the SPI/I
receive buffer SFR (SPI2CRx, Address 0x9B).
Note that the SPI pins are shared with the I
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF) selects which peripheral
is active.
Description
SPI/I
SPI/I
SPI Configuration SFR 1 (see Table 153).
SPI Configuration SFR 2 (see Table 154).
SPI interrupt status (see Table 155).
2
2
C transmit buffer (see Table 151).
C receive buffer (see Table 152).
2
C bus is written to the FIFO input.
ADE5166/ADE5169
2
C bus.
2
C pins. Therefore, the
2
C
2
C