ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 135

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

SS (Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of SS
low. The SPI port then transmits and receives 8-bit data until
the data is concluded by the deassertion of SS according to the
SPICON bit setting. In slave mode, SS is always an input.
In SPI master mode, the SS (P0.7/ SS /T1/RxD2) pin can be used
to control data transfer to a slave device. In the automatic slave
select control mode, the SS is asserted low to select the slave
device and then raised to deselect the slave device after the
transfer is complete. Automatic slave select control is enabled by
setting the AUTO_SS bit (Bit 4) in the SPI Configuration SFR 1
(SPIMOD1, Address 0xE8).
In a multimaster system, the SS can be configured as an input so
that the SPI peripheral can operate as a slave in some situations
and as a master in others. In this case, the slave selects for the
slaves controlled by this SPI peripheral should be generated
with general I/O pins.
SPI MASTER OPERATING MODES
The double-buffered receive and transmit registers can be used to
maximize the throughput of the SPI peripheral by continuously
streaming out data in master mode. The continuous transmit mode
is designed to use the full capacity of the SPI. In this mode, the
master transmits and receives data until the SPI/I2C transmit
buffer SFR (SPI2CTx, Address 0x9A) is empty at the start of a byte
transfer. Continuous mode is enabled by setting the SPICONT bit
(Bit 7) in the SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).
The SPI peripheral also offers a single byte read/write function.
In master mode, the type of transfer is handled automatically,
depending on the configuration of the SPICONT bit in the SPI
Configuration SFR 2 (SPIMOD2, Address 0xE9). The following
procedures show the sequence of events that should be performed
for each master operating mode. Based on the SS configuration,
some of these events take place automatically.
Procedures for Using SPI as a Master
Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0
1.
2.
3.
4.
5.
Write to the SPI2CTx SFR.
SS is asserted low, and a write routine is initiated.
The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
SS is deasserted high.
Write to SPI2CTx SFR to clear the SPITxIRQ interrupt flag.
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Continuous Mode, SPICONT (SPIMOD2[7]) = 1
1.
2.
3.
4.
5.
6.
7.
Figure 106 shows the SPI output for certain automatic chip select
and continuous mode selections. Note that if the continuous mode
is not used, a short delay is inserted between transfers.
Note that reading the content of the SPI/I
(SPI2CRx, Address 0x9B) should be done using a 2-cycle
instruction set, such as MOV A or SPI2CRX. Using a 3-cycle
instruction, such as MOV 0x3D or SPI2CRX, does not transfer
the right information into the target register.
(MANUAL SS CONTROL)
Write to the SPI2CTx SFR.
SS is asserted low, and a write routine is initiated.
Wait for the SPITxIRQ interrupt flag to write to SPI2CTx SFR.
Transfer continues until the SPI2CTx register and transmit
shift registers are empty.
The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
SS is deasserted high.
Write to SPI2CTx SFR to clear the SPITxIRQ interrupt flag.
Figure 106. Automatic Chip Select and Continuous Mode Output
AUTO_SS = 1
AUTO_SS = 1
AUTO_SS = 0
SPICONT = 1
SPICONT = 0
SPICONT = 0
DOUT
SCLK
DOUT
DOUT
SCLK
SCLK
DIN
SS
DIN
DIN
SS
SS
DOUT1
ADE5166/ADE5169
DOUT1
DIN1
DIN1
DOUT1
DIN1
2
C receive buffer SFR
DOUT2
DIN2
DOUT2
DOUT2
DIN2
DIN2