ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 64

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Figure 72 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy theoretically remains positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register (Address 0x26) is 0, the internal
apparent energy register is divided by 1. VADIV is an 8-bit,
unsigned register. The upper 24 bits are then written in the 24-bit
apparent energy register (VAHR[23:0], Address 0x07). The
RVAHR register (Address 0x08), which is 24 bits long, is provided
to read the apparent energy. This register is reset to 0 after a read
operation.
Note that the apparent energy register is unsigned. By setting
the VAEHF bit (Bit 2) and the VAEOF bit (Bit 5) in the Interrupt
Enable 2 SFR (MIRQENM, Address 0xDA), the ADE5166/
ADE5169 can be configured to issue an ADE interrupt to the
8052 core when the apparent energy register is half-full or when
an overflow occurs. The half-full interrupt for the unsigned
apparent energy register is based on 24 bits, as opposed to 23 bits
for the signed active energy register.
Integration Times Under Steady Load: Apparent Energy
As mentioned in the Apparent Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the
APPARENT POWER
I
rms
or
T
APPARENT
POWER SIGNAL = P
Figure 72. Apparent Energy Calculation
TIME (nT)
+
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+
48
48
23
VADIV
VAHR[23:0]
analog inputs and the VAGAIN register (Address 0x1F) set to
0x000, the average word value from the apparent power stage is
0x1A36E2 (see the Apparent Power Calculation section). The
maximum value that can be stored in the apparent energy register
before it overflows is 2
is added to the internal register, which can store 2
0xFFFF,FFFF,FFFF before it overflows. Therefore, the integration
time under these conditions with VADIV = 0 is calculated as
follows:
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 35.
Apparent Energy Pulse Output
All the ADE5166/ADE5169 circuitry has a pulse output whose
frequency is proportional to apparent power (see the Energy-to-
Frequency Conversion section). This pulse frequency output
uses the calibrated signal after VAGAIN. This output can also
be used to output a pulse whose frequency is proportional to I
The pulse output is active low and should preferably be connected
to an LED, as shown in Figure 75.
APPARENT POWER OR I
ACCUMULATED (INTEGRATED)
IN THE APPARENT ENERGY
REGISTER
%
Time =
Time = Time
0xFFFF,
0
0xD055
FFFF,
WDIV = 0
FFFF
0
0
rms
24
or 0xFF,FFFF. The average word value
× VADIV
IS
×
. 1
22
μ
s
=
199
sec
=
. 3
48
33
or
min
(34)
(35)
rms
.