ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 22

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
SPECIAL FUNCTION REGISTER (SFR) MAPPING
Table 14. SFR Mapping
Mnemonic
INTPR
SCRATCH4
SCRATCH3
SCRATCH2
SCRATCH1
BATVTH
STRBPER
IPSMF
TEMPCAL
RTCCOMP
BATPR
PERIPH
DIFFPROG
B
VDCINADC
SBAUD2
LCDSEGE2
IPSME
SBUF2
SPISTAT
SPI2CSTAT
SPIMOD2
I2CADR
SPIMOD1
I2CMOD
WAV2H
WAV2M
WAV2L
WAV1H
WAV1M
WAV1L
SCON2
ACC
BATADC
MIRQSTH
MIRQSTM
MIRQSTL
MIRQENH
MIRQENM
0xFF
0xF8
0xF7
0xF5
0xF4
0xEF
0xED
0xEC
0xE7
0xE5
0xE4
0xE2
0xDE
0xDC
0xDB
0xDA
Address
0xFE
0xFD
0xFC
0xFB
0xFA
0xF9
0xF6
0xF3
0xF0
0xEE
0xEB
0xEA
0xEA
0xE9
0xE9
0xE8
0xE8
0xE6
0xE3
0xE1
0xE0
0xDF
0xDD
Description
Interrupt pins configuration SFR (see
Table 16).
Scratch Pad 4 (see Table 24).
Scratch Pad 3 (see Table 23).
Scratch Pad 2 (see Table 22).
Scratch Pad 1 (see Table 21).
Battery detection threshold (see
Table 52).
Peripheral ADC strobe period (see
Table 49).
Power management interrupt flag (see
Table 17).
RTC temperature compensation (see
Table 132).
RTC nominal compensation (see
Table 131).
Battery switchover configuration (see
Table 18).
Peripheral configuration (see Table 19).
Temperature and supply delta (see
Table 50).
Auxiliary math (see Table 56).
V
Enhanced Serial Baud Rate Control 2
(see Table 148).
LCD Segment Enable 2 (see Table 100).
Power management interrupt enable
(see Table 20).
Serial Port 2 buffer (see Table 147).
SPI interrupt status (see Table 155).
I
SPI Configuration SFR 2 (see Table 154).
I
SPI Configuration SFR 1 (see Table 153).
I
Selection 2 sample MSB (see Table 30).
Selection 2 sample middle byte (see
Table 30).
Selection 2 sample LSB (see Table 30).
Selection 1 sample MSB (see Table 30).
Selection 1 sample middle byte (see
Table 30).
Selection 1 sample LSB (see Table 30).
Serial communications control (see
Table 146).
Accumulator (see Table 56).
Battery ADC value (see Table 54).
Interrupt Status 3 (see Table 42).
Interrupt Status 2 (see Table 41).
Interrupt Status 1 (see Table 40).
Interrupt Enable 3 (see Table 45).
Interrupt Enable 2 (see Table 44).
2
2
2
DCIN
C interrupt status (see Table 159).
C slave address (see Table 158).
C mode (see Table 157).
ADC value (see Table 53).
Rev. 0 | Page 22 of 148
Mnemonic
MIRQENL
ADCGO
TEMPADC
IRMSH
IRMSM
IRMSL
VRMSH
VRMSM
VRMSL
PSW
TH2
TL2
RCAP2H
RCAP2L
T2CON
EADRH
EADRL
POWCON
KYREG
WDCON
STCON
EDATA
PROTKY
FLSHKY
ECON
IP
SPH
PINMAP2
PINMAP1
PINMAP0
LCDCONY
CFG
LCDDAT
LCDPTR
IEIP2
IE
DPCON
RTCDAT
RTCPTR
TIMECON2
TIMECON
P2
EPCFG
Address
0xD9
0xD8
0xD7
0xD6
0xD5
0xD4
0xD3
0xD2
0xD1
0xD0
0xCD
0xCC
0xCB
0xCA
0xC8
0xC7
0xC6
0xC5
0xC1
0xC0
0xBF
0xBC
0xBB
0xBA
0xB9
0xB8
0xB7
0xB4
0xB3
0xB2
0xB1
0xAF
0xAE
0xAC
0xA9
0xA8
0xA7
0xA4
0xA3
0xA2
0xA1
0xA0
0x9F
Description
Interrupt Enable 1 (see Table 43).
Start ADC measurement (see Table 51).
Temperature ADC value (see Table 55).
I
I
Table 30).
I
V
V
Table 30).
V
Program status word (see Table 57).
Timer 2 high byte (see Table 119).
Timer 2 low byte (see Table 120).
Timer 2 reload/capture high byte (see
Table 121).
Timer 2 reload/capture low byte (see
Table 122).
Timer/Counter 2 control (see Table 114).
Flash high byte address (see Table 109).
Flash low byte address (see Table 108).
Power control (see Table 25).
Key (see Table 125).
Watchdog timer (see Table 87).
Stack boundary (see Table 64).
Flash data (see Table 107).
Flash protection key (see Table 106).
Flash key (see Table 105).
Flash control (see Table 104).
Interrupt priority (see Table 81).
Stack pointer high (see Table 63).
Port 2 weak pull-up enable (see
Table 164).
Port 1 weak pull-up enable (see
Table 163).
Port 0 weak pull-up enable (see
Table 162).
LCD Configuration Y (see Table 93).
Configuration (see Table 65).
LCD data (see Table 99).
LCD pointer (see Table 98).
Interrupt enable and Priority 2 (see
Table 82).
Interrupt enable (see Table 80).
Data pointer control (see Table 78).
RTC pointer data (see Table 130).
RTC pointer address (see Table 129).
RTC Configuration 2 (see Table 128).
RTC configuration (see Table 127).
Port 2 (see Table 167).
Extended port configuration (see
Table 161).
rms
rms
rms
rms
rms
rms
measurement MSB (see Table 30).
measurement middle byte (see
measurement LSB (see Table 30).
measurement MSB (see Table 30).
measurement middle byte (see
measurement LSB (see Table 30).