CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 9

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 001-15013 Rev. *H
A
BW
BW
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
ZZ
DQ
DQP
MODE
V
V
V
TDO
0
DD
DDQ
SS
, A
1
2
3
s
A
C
E
G
Name
, BW
, BW
, BW
X
, BW
1
, A
B
F
H
D
,
,
,
JTAG serial output
IO Power Supply
Input Strap Pin
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
IO-
IO-
IO
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK. A
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD must
be driven LOW to load a new address.
Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic
block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled
to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins.
OE is masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does
not deselect the device, CEN can be used to extend the previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin must be LOW or left
floating. ZZ pin has an internal pull down.
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQ
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ
write sequences, DQP
Mode Input. Selects the Burst Order of the Device.
When tied to Gnd selects linear burst sequence. When tied to V
leaved burst sequence.
Power Supply Inputs to the Core of the Device.
Power Supply for the IO Circuitry.
Ground for the Device.
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not used, this pin must be left unconnected. This pin is not available on TQFP
packages.
2
1
1
and CE
and CE
and CE
[1:0]
3
2
3
s
are fed to the two-bit burst counter.
to select or deselect the device.
to select or deselect the device.
to select or deselect the device.
and DQP
X
is controlled by BW
X
are placed in a tri-state condition.The outputs are automatically
CY7C1473BV25, CY7C1475BV25
Description
X
correspondingly.
DD
or left floating selects inter-
CY7C1471BV25
Page 9 of 33
s
. During
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