CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 14

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
incorporate a serial boundary scan Test Access Port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5 V IO logic levels.
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
contain a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (V
prevent clocking of the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be connected
to V
During power up, the device comes up in a reset state, which
does not interfere with the operation of the device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Document Number: 001-15013 Rev. *H
DD
1
0
through a pull up resistor. TDO must be left unconnected.
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
1
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCA N
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
SS
1
1
0
0
) to
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data In (TDI)
The TDI ball serially inputs information into the registers and is
connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the
TDI is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant
bit (MSB) of any register. (See
Test Data Out (TDO)
The TDO output ball serially clocks data out from the registers.
The output is active depending upon the current state of the TAP
state machine. The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register.
(See
TAP Controller Block Diagram
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
During power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TM S
TCK
TDI
TAP Controller State
CY7C1473BV25, CY7C1475BV25
Selection
Circuitry
Boundary Scan Register
Identification Register
31
x
Instruction Register
TAP CONTROLLER
Diagram.)
30
.
Bypass Register
29
.
.
.
TAP Controller Block
.
.
TAP Controller State
.
.
2
2
2
CY7C1471BV25
1
1
1
0
0
0
0
Selection
Circuitry
DD
Page 14 of 33
) for five rising
Diagram.)
Diagram.
TDO
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