CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 23

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-15013 Rev. *H
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
17. Timing reference level is 1.25 V when V
18. Test conditions shown in (a) of
19. This part has a voltage regulator internally; t
20. t
21. At any supplied voltage and temperature, t
22. This parameter is sampled and not 100% tested.
POWER
CYC
CH
C]L
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
CHZ
, t
Parameter
[19]
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of
[17, 18]
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low Z
Clock to High Z
OE LOW to Output Valid
OE LOW to Output Low Z
OE HIGH to Output High Z
Address Setup Before CLK Rise
ADV/LD Setup Before CLK Rise
WE, BW
CEN Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BW
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
Figure 4 on page 22
DDQ
X
X
OEHZ
POWER
Setup Before CLK Rise
Hold After CLK Rise
= 2.5 V.
is less than t
[20, 21, 22]
is the time that the power is supplied above V
[20, 21, 22]
unless otherwise noted.
Description
OELZ
[20, 21, 22]
and t
[20, 21, 22]
CHZ
is less than t
Figure 4 on page
CLZ
to eliminate bus contention between SRAMs when sharing the same data
CY7C1473BV25, CY7C1475BV25
DD
(minimum) initially, before a read or write operation can be initiated.
Min
22. Transition is measured ±200 mV from steady-state voltage.
7.5
2.5
2.5
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
133 MHz
Max
6.5
3.8
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
2.5
1.5
3.0
3.0
3.0
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
–
–
–
0
–
CY7C1471BV25
100 MHz
Max
8.5
4.5
3.8
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 23 of 33
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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