CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 10

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Functional Overview
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
are synchronous flow through burst SRAMs designed
specifically to eliminate wait states during write read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (t
device).
Accesses are initiated by asserting all three Chip Enables (CE
CE
LOW and ADV/LD is asserted LOW, the address presented to
the device is latched. The access is either a read or write
operation, depending on the status of the Write Enable (WE).
Use Byte Write Select (BW
Write operations are qualified by the WE. All writes are simplified
with on-chip synchronous self- timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise:
■
■
■
■
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
Document Number: 001-15013 Rev. *H
TDI
TMS
TCK
NC
CEN is asserted LOW
CE
WE is deasserted HIGH
ADV/LD is asserted LOW.
2
, CE
Name
1
, CE
3
) active at the rising edge of the clock. If CEN is active
2
, and CE
JTAG serial input
JTAG serial input
Synchronous
Synchronous
JTAG-Clock
3
(continued)
are ALL asserted active
IO
-
X
) to conduct Byte Write operations.
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not used, leave this pin floating or connected to V
available on TQFP packages.
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not used, this pin can be disconnected or connected to V
packages.
Clock Input to the JTAG Circuitry. If the JTAG feature is not used, connect this pin to V
This pin is not available on TQFP packages.
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
CDV
1
) is 6.5 ns (133-MHz
, CE
2
, CE
3
) and an
1
,
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, the
output is tri-stated immediately.
Burst Read Accesses
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
has an on-chip burst counter that enables the user the ability to
supply a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD must be driven LOW to
load a new address into the SRAM, as described in the
Read Accesses
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enable inputs or WE. WE is latched
at the beginning of a burst cycle. Therefore, the type of access
(read or write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when these conditions are satisfied
at clock rise:
■
■
■
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP
On the next clock rise the data presented to DQs and DQP
a subset for Byte Write operations, see
Read/Write on page 13
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BW
signals.
CY7C1475BV25 provide Byte Write capability that is described
in the
the selected BW
bytes. Bytes not selected during a Byte Write operation remain
unaltered. A synchronous self timed write mechanism is
CEN is asserted LOW
CE
WE is asserted LOW.
1
Truth Table for Read/Write on page
, CE
CY7C1473BV25, CY7C1475BV25
Description
2
The
, and CE
section. The sequence of the burst counter is
x
CY7C1471BV25,
DD
input selectively writes to only the desired
3
are ALL asserted active
through a pull up resistor. This pin is not
for details) inputs is latched into the
DD
. This pin is not available on TQFP
CY7C1471BV25
CY7C1473BV25,
13. The input WE with
Truth Table for
Page 10 of 33
X
.
Single
X
and
SS
(or
.
X
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