CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 25

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 6
Notes
Document Number: 001-15013 Rev. *H
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE
28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
COMMAND
ADDRESS
ADV/LD
BW
shows NOP, STALL and DESELECT Cycles waveform.
CEN
CLK
[A:D]
WE
DQ
CE
1
WRITE
D(A1)
is LOW, CE
A1
1
D(A1)
2
(continued)
Q(A2)
READ
is HIGH, and CE
A2
2
Figure 6. NOP, STALL and DESELECT Cycles
STALL
3
3
is LOW. When CE is HIGH, CE
Q(A2)
READ
Q(A3)
A3
4
DON’T CARE
[26, 27, 28]
WRITE
D(A4)
A4
Q(A3)
5
1
is HIGH, CE
STALL
UNDEFINED
6
CY7C1473BV25, CY7C1475BV25
2
is LOW or CE
D(A4)
NOP
7
3
is HIGH.
Q(A5)
READ
A5
8
t DOH
CY7C1471BV25
DESELECT
Q(A5)
9
t CHZ
CONTINUE
DESELECT
Page 25 of 33
10
[+] Feedback