CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 18

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Identification Register Definitions
Scan Register Sizes
Identification Codes
Document Number: 001-15013 Rev. *H
Revision Number (31:29)
Device Depth (28:24)
Architecture/Memory Type (23:18)
Bus Width/Density (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Instruction
Bypass
ID
Boundary Scan Order – 165-ball FBGA
Boundary Scan Order – 209-ball BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction Field
Instruction
Register Name
Code
CY7C1471BV25
000
001
010
100
101
011
110
111
00000110100
(2 M × 36)
001001
100100
01011
000
1
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
Do Not Use: This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Bit Size (× 36)
32
71
3
1
–
CY7C1473BV25
00000110100
(4 M × 18)
001001
010100
01011
000
1
CY7C1475BV25
00000110100
Bit Size (× 18)
CY7C1473BV25, CY7C1475BV25
(1 M × 72)
001001
110100
01011
000
1
32
52
3
1
–
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM
vendor
Indicates the presence of an ID register
CY7C1471BV25
Description
Bit Size (× 72)
110
32
3
1
–
Page 18 of 33
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