CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 11

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

provided to simplify the write operations. Byte Write capability is
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
Because
CY7C1475BV25 are common IO devices, data must not be
driven into the device while the outputs are active. The OE can
be deasserted HIGH before presenting data to the DQs and
DQP
precaution, DQs and DQP
the data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
have an on-chip burst counter that makes it possible to supply a
single address and conduct up to four Write operations without
reasserting the address inputs. Drive ADV/LD LOW to load the
initial address, as described in the
section. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE
ignored and the burst counter is incremented. You must drive the
correct BW
correct data bytes.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. You must
select the device before entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Document Number: 001-15013 Rev. *H
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
X
inputs. This tri-states the output drivers. As a safety
3
, must remain inactive for the duration of t
X
the
inputs in each cycle of the Burst Write to write the
CY7C1471BV25,
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
1
X
, CE
are automatically tri-stated during
2
, and CE
Description
CY7C1473BV25,
Single Write Accesses
3
) and WE inputs are
ZZREC
after the
1
, CE
and
2
,
This parameter is sampled
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table
(MODE = GND)
Address
Address
Test Conditions
DD
DD
A1: A0
A1: A0
First
First
00
01
10
00
01
10
– 0.2 V
11
11
– 0.2 V
CY7C1473BV25, CY7C1475BV25
Address
Address
Second
Second
A1: A0
A1: A0
01
00
11
10
01
10
11
00
2t
DD
Min
CYC
–
–
–
0
Address
Address
)
A1: A0
A1: A0
Third
Third
CY7C1471BV25
10
11
00
01
10
11
00
01
2t
2t
Max
120
CYC
CYC
–
–
Page 11 of 33
Address
Address
Fourth
A1: A0
Fourth
A1: A0
10
01
00
00
01
10
11
11
Unit
mA
ns
ns
ns
ns
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