CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 16

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

no guarantee as to the value that is captured. Repeatable results
may not be possible.
To guarantee that the boundary scan register captures the
correct signal value, make certain that the SRAM signal is
stabilized long enough to meet the TAP controller’s capture
setup plus hold time (t
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Document Number: 001-15013 Rev. *H
Test M ode Select
Test Data-Out
Test Data-In
Test Clock
CS
plus t
(TDO)
(TM S)
(TCK )
(TDI)
CH
).
1
t TM SS
t TDIS
Figure 3. TAP Timing
2
t TM SH
t TDIH
t TH
DON’T CA RE
t
TL
3
Note that since the PRELOAD part of the command is not imple-
mented, putting the TAP to the Update-DR state while performing
a SAMPLE/PRELOAD instruction has the same effect as the
Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CY C
CY7C1473BV25, CY7C1475BV25
UNDEFINED
4
t TDOX
t TDOV
5
6
CY7C1471BV25
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