CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet - Page 24

• Manufacturer Part Number: CY7C1471BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 5
Notes
Document Number: 001-15013 Rev. *H
23. For this waveform ZZ is tied LOW.
24. When CE is LOW, CE
25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
COM M AND
ADDRESS
ADV/LD
shows read-write timing waveform.
BW
CEN
CLK
W E
DQ
OE
CE
X
t CENS
t CES
t AS
1
W RITE
D(A1)
A1
is LOW, CE
1
t CENH
t CEH
t AH
t DS
2
W RITE
D(A1)
D(A2)
is HIGH, and CE
A2
2
t CH
t DH
t CYC
t CL
D(A2+1)
D(A2)
BURST
W RITE
[23, 24, 25]
3
3
is LOW. When CE is HIGH, CE
Figure 5. Read/Write Timing
DON’T CARE
D(A2+1)
READ
Q(A3)
A3
4
t CDV
t CLZ
Q(A4)
READ
Q(A3)
A4
5
t DOH
1
t OEHZ
is HIGH, CE
UNDEFINED
Q(A4+1)
BURST
Q(A4)
READ
CY7C1473BV25, CY7C1475BV25
6
2
t OEV
is LOW or CE
t OELZ
Q(A4+1)
W RITE
D(A5)
A5
7
t CHZ
t DOH
3
is HIGH.
READ
Q(A6)
A6
D(A5)
8
CY7C1471BV25
W RITE
D(A7)
Q(A6)
A7
9
Page 24 of 33
DESELECT
D(A7)
10
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