h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 536
h8s-2161b
Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2161B.pdf
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Section 16 I
9. Note on when I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
Rev. 3.00 Mar 21, 2006 page 482 of 788
REJ09B0300-0300
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
ICXR.
SDA
IRIC
SCL
2
C Bus Interface (IIC) (Optional)
2
C bus interface stop condition instruction is issued
VIH
9th clock
Figure 16.32 Stop Condition Issuance Timing
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination
Secures a high period
[2] Stop condition instruction issuance
Stop condition generation
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