h8s-2161b Renesas Electronics Corporation., h8s-2161b Datasheet - Page 573
h8s-2161b
Manufacturer Part Number
h8s-2161b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2161B.pdf
(845 pages)
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Table 18.2 shows the conditions for setting and clearing the STR flags.
Table 18.2 Set/Clear Timing for STR Flags
Note:
18.4
18.4.1
The host interface is activated by setting the HI12E bit in SYSCR2 to 1 in single-chip mode.
When the host interface is activated, all related I/O ports (data port 3, control ports 8 and 9, and
host interrupt request port 4) become dedicated host interface ports. Setting the CS3E bit and
CS4E bit to 1 enables the number of host interface channels to be extended to four, and makes the
channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated
host interface port.
Flag
C/D
IBF *
OBF
* The IBF flag setting and clearing conditions are different when the fast A20 gate is
Operation
Host Interface Activation
used. For details see table 18.5.
Setting Condition
Rising edge of host’s write signal
(IOW) when HA0 is high
Rising edge of host’s write signal
(IOW) when writing to IDR1
Falling edge of slave’s internal write
signal when writing to ODR1
Section 18 Host Interface X-Bus Interface (XBS)
Clearing Condition
Rising edge of host’s write signal (IOW) when
HA0 is low
Falling edge of slave’s internal read signal
when reading IDR1
Rising edge of host’s read signal (IOR) when
reading ODR1
Rev. 3.00 Mar 21, 2006 page 519 of 788
REJ09B0300-0300
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