nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 97

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
9.3
When an enabled interrupt occurs, the MCU vectors to the address of the interrupt service routine (ISR)
associated with that interrupt, as listed in
another interrupt of higher priority occurs.
9.4
Various SFR registers are used to control and prioritize between different interrupts.
The TCON , IRCON , SCON , IP0 , IP1 , IEN0 , IEN1 and INTEXP are described in this section. In addition the
TCON and T2CON are used, the description for these registers can be found in
Revision 1.1
WIRE2IRQ
WUOPIRQ
MSDONE
SSDONE
MISCIRQ
POFIRQ
Source
Note: When XOSC16M has started, X16IRQ blocks the IRQ control of ADC and RNG. In this case it
Note: RFIRQ , WUOPIRQ , MISCIRQ and TICK are not activated unless wakeup is enabled by WUCON
RFRDY
RFIRQ
TICK
exf2
IFP
tf0
tf1
ri0
ti0
tf2
Functional description
SFR registers
is recommended to disable X16IRQ by clearing CLKCTRL.3. XOSC16M startup can still be
polled (see the CLKCTRL description in
(see
section 11.3.5 on page
0x000B
0x001B
0x002B
0x002B
0x004B
0x005B
0x006B
vector
0x0003
0x0013
0x0023
0x0023
0x0043
0x0053
0x0053
0x0053
0x0063
Polarity
fall/rise
fall/rise
fall/rise
fall/rise
low/fall
low/fall
High
high
high
high
high
high
high
rise
rise
rise
Table 46. nRF24LE1 interrupt sources.
Interrupt from pin
Timer 0 overflow interrupt
Power Failure interrupt
Timer 1 overflow interrupt
Serial channel receive interrupt
Serial channel transmit interrupt
Timer 2 overflow interrupt
Timer 2 external reload
RF SPI ready
RF IRQ
Master SPI transaction completed
2-Wire transaction completed
Slave SPI transaction completed
Wakeup on pin interrupt
Miscellaneous interrupt is the sum of:
Internal Wakeup (from RTC2) interrupt
110).
T able 46.
8 5 5 H
•
•
•
XOSC16M started (X16IRQ)
ADC Ready (ADCIRQ) interrupt
RNG ready (RNGIRQ) interrupt
97 of 191
The MCU executes the ISR to completion unless
section 11.3.1 on page
Description
106).
chapter 8 on page
85.