nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 89

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nrf24le1-f16q48-t

Manufacturer Part Number
nrf24le1-f16q48-t
Description
Ultra-low Power Wireless System On-chip Solution
Manufacturer
ETC-unknow
Datasheet
nRF24LE1 Preliminary Product Specification
Timer 2 is incremented every 12 or 24 clock cycles depending on the 2:1 prescaler. The prescaler mode is
selected by bit t2ps of T2CON register. When t2ps=0, the timer counts up every 12 clock cycles, otherwise
every 24 cycles.
8.3.2.3
This mode is invoked by setting the t2i0=0 and t2i1=1 in the T2CON register.
In this mode, Timer 2 is incremented when external signal T2 (see
mation on T2) changes its value from 1 to 0. The T2 input is sampled at every rising edge of the clock.
Timer 2 is incremented in the cycle following the one in which the transition was detected. The maximum
count rate is ½ of the clock frequency.
8.3.2.4
This mode is invoked by setting the t2i0=1 and t2i1=1 in the T2CON register.
In this mode, Timer 2 is incremented every 12 or 24 clock cycles (depending on T2CON t2ps flag). Addi-
tionally, it is gated by the external signal T2. When T2=0, Timer 2 is stopped.
8.3.2.5
A 16-bit reload from the CRC register can be done in two modes:
8.4
8.4.1
TCON register reflects the current status of MCU Timer 0 and Timer 1 and it is used to control the operation
of these modules.
Revision 1.1
Address
0x88
Reload Mode 0: Reload signal is generated by Timer 2 overflow (auto reload).
Reload Mode 1: Reload signal is generated by negative transition at t2ex.
Note: t2ex is connected to an internal clock signal which is half frequency of CLKLF (see
SFR registers
Timer/Counter control register – TCON
11.3.1 on page
Reset
value
Event counter mode
Gated timer mode
Timer 2 reload
0x00
Bit Name
7
6
5
4
3
2
1
0
106.)
ie1
ie0
tr1
tr0
tf1
tf0
it1
it0
clear
Auto
Yes
Yes
Yes
Yes
No
No
No
No
Table 36. TCON register
Timer 1 overflow flag. Set by hardware when Timer1 over-
flows.
Timer 1 Run control. If cleared, Timer 1 stops.
Timer 0 overflow flag. Set by hardware when Timer 0 over-
flows.
Timer 0 Run control. If cleared, Timer 0 stops.
External interrupt 1 flag. Set by hardware.
External interrupt 1 type control. 1: falling edge, 0: low level
External interrupt 0 flag. Set by hardware.
External interrupt 0 type control. 1: falling edge, 0: low level
89 of 191
section 8.4 on page 89
Description
for more infor-
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