nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 120

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
The ARCON register controls the operation of MDU and informs you about its current state.
The operation of the MDU consists of the following phases:
14.4.1
The type of calculation the MDU has to perform is selected in accordance with the order in which the MDx
registers are written.
The SFR Control detects some of the above sequences and passes control to the MDU. When a write
access occurs to MD2 or MD3 between write accesses to MD0 and finally to MD5, then a 32/16 bit division
is selected.
When a write access to MD4 or MD1 occurs before writing to MD5, then a 16/16 bit division or 16x16 bit
multiplication is selected. Writing to MD4 selects 16/16 bit division and writing to MD1 selects 16x16 bit
multiplication, that is, Num1 x Num2.
Revision 1.1
Address Reset value Bit Name
Operation
1.
2.
3.
first write
last write
0xEF
Write MD0 to start any operation.
Write operations, as shown in
Write (to MD5 or ARCON) starts selected operation.
Loading the MDx registers
0x00
MD3 (msb)
MD5 (msb)
MD0 (lsb)
MD4 (lsb)
32 bit/16 bit
MD1
MD2
4-0
7
6
5
mdov MDU Overflow flag MDOV. Overflow occurrence in the MDU oper-
mdef MDU Error flag MDEF. Indicates an improperly performed opera-
slr
sc
Table 68. MDU registers write sequence
MD1 (msb)
MD5 (msb)
MD0 (lsb)
MD4 (lsb)
tion (when one of the arithmetic operations has been restarted or
interrupted by a new operation).
ation.
Shift direction, 0: shift left, 1: shift right.
Shift counter. When set to ‘0’s, normalize operation is selected.
After normalization, the “sc.0” … “sc.4” contains the number of
normalizing shifts performed.
Shift operation is selected when at least one of these bits is set
high. The number of shifts performed is determined by the num-
ber written to “sc.4”.., “sc.0”, where “sc.4” is the MSB.
16 bit / 16 bit
Table 68.
Table 67. ARCON register
120 of 191
to determine appropriate MDU operation.
MD1 (msb)
MD5 (msb)
MD0 (lsb)
MD4 (lsb)
16 bit x 16 bit
Description
Num1
Num2
Num1
Num2
MD3 (msb)
MD0 (lsb)
Shift/normalize
ARCON
MD1
MD2