nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 145

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
18.3.2
The following registers control the SPI slave:
Revision 1.1
Address
(Hex)
0xBC
0xBD
0xBE
Name/mnemonic
maskIrqScsnHigh
maskIrqScsnLow
SPI slave
spiSlaveConfig0
spiSlaveEnable
maskIrqTxFifo-
spiSlaveStatus
maskIrqRxDa-
clockPolarity
SPISCON0
clockPhase
SPISSTAT
dataOrder
Reserved
Reserved
Reserved
Reserved
scsnHigh
taReady
Ready
Bit
7:0
7:0
7:2
5:0
7
6
5
4
3
2
1
0
1
0
5
Reset
value
0xF0
0x0F
0x03
0x03
1
1
1
1
0
0
0
0
1
1
0
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Type
R/W Defines the SPI Slave’s operating mode
R/W Defines the SPI Slave’s operating mode
R/W 1: SPI Slave is enabled. The clock to the SPI
R/W SPI Slave configuration register 0.
R/W Only “1” allowed.
R/W 1: Disable interrupt when data is available in RX
R/W Only “1” allowed.
R/W 1: Disable interrupt when a location is available
R/W Data order (bit wise per byte) on serial input and
R/W Only “0x0F” allowed.
R/W Only “0x03” allowed.
R/W 1: Disable interrupt when SCSN goes ‘high’.
R/W 1: Disable interrupt when SCSN goes ‘low’.
R
R
FIFO.
0: Enable interrupt when data is available in RX
FIFO.
in TX FIFO.
0: Enable interrupt when a location is available
in TX FIFO.
output (SMOSI and SMISO respectively).
1: LSBit first, MSBit last.
0: MSBit first, LSBit last.
together with with SPISCON0.1, see chapter
18.3.3 SPI timing.
1: SSCK is active ‘low’.
0: SSCK is active ‘high’.
together with with SPISCON0.2, see chapter
18.3.3 SPI timing.
1: Sample on trailing edge of SSCK, shift on
leading edge.
0: Sample on leading edge of SSCK, shift on
trailing edge.
Slave core functionality is running. An SPI trans-
fer can be initiated by an SPI Master (RX).
0: SPI Slave is disabled. The clock to the SPI
Slave core functionality stands still.
0: Enable interrupt when SCSN goes ‘high’.
0: Enable interrupt when SCSN goes ‘low’.
SPI Slave status register.
Interrupt source.
1: Positive edge of SCSN detected.
0: Positive edge of SCSN not detected.
Cleared when read.
Description