nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 156

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
20.2.3.1
Revision 1.1
SDA
SCL
f
CK
SCL
RIOD
t
t
t
t
t
t
P
t
RT
t
WIRQ
P2IRQ
CK
STA2SCL0
SCL0F
DSETUP
DHOLD
SCL0L
SCL12STO
STOP2STA
REL
Symbol
PERIOD
PE-
2-Wire timing
t(STA2SCL0)
t(SCL0F)
t(SCL0F)
System clock frequency.
System clock period.
SCL clock period.
Time from start condition to SCL
goes ‘low’.
SCL ‘low’ time after start condition.
Data setup time before positive edge
on SCL.
Data hold time after negative edge
on SCL.
SCL ‘low’ time after last bit before
stop condition.
Time from SCL goes ‘high’ to stop
condition.
Time from stop condition to start
condition.
Time from change on SDA until SCL
is released when the module is a
Slave that forces SCL ‘low’.
Width of IRQ signal.
Time from positive edge on SCL to
IRQ signal.
Parameter (CK = 16MHz)
t(DSETUP)
Table 96. Timing (16MHz system clock)
SCL(PERIOD)
SCL(PERIOD)
Figure 65. Timing SCL/SDA
t(DHOLD)
156 of 191
4· CK
9· CK
10000
3·CK
5000
4400
5000
5000
4700
1400
Min
62.5
Standard
16
P
P
P
Max
4700
560
3· CK
4· CK
8· CK
2500
1250
1250
1300
1000
1400
Min
62.5
800
16
Fast
P
P
P
t(SCLOL)
t(SCLOL)
Max
940
440
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t(SCL12