nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 43

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
3.5
The data and control interface gives you access to all the features in the RF Transceiver. Compared to the
standalone component SFR registers are used instead of port pins. Otherwise the interface is identical to
the standalone nRF24L01+ chip.
3.5.1
Revision 1.1
Address
•
(Hex)
0xE4
0xE5
0xE6
0xE7
The CRC is optional in the ShockBurst™ packet format and is controlled by the EN_CRC bit in the
CONFIG register.
Data and control interface
SFR registers
Name/Mnemonic
maskIrqRxFifoFull
spiMasterConfig0
spiMasterConfig1
spiMasterStatus
maskIrqTxFifo-
maskIrqRxDa-
spiMasterData
maskIrqTxFi-
rxDataReady
txFifoEmpty
txFifoReady
SPIRCON0
SPIRCON1
SPIRSTAT
SPIRDAT
rxFifoFull
taReady
foEmpty
Ready
Table 8. RF Transceiver SPI master registers
Bit
6:0
3:0
3:0
7:0
3
2
1
0
3
2
1
0
Reset
value
0x01
0x0F
0x03
0x00
1
0
0
1
1
1
1
1
Type
R/W SPI Master configuration register 0.
R/W SPI Master configuration register 1.
R/W 1: Disable interrupt when RX FIFO is full.
R/W 1: Disable interrupt when data is available in RX
R/W 1: Disable interrupt when TX FIFO is empty.
R/W 1: Disable interrupt when a location is available in
R/W SPI Master data register.
43 of 191
R
R
R
R
R
Interrupt source.
Interrupt source.
Reserved. Do not alter.
0: Enable interrupt when RX FIFO is full.
FIFO.
0: Enable interrupt when data is available in RX
FIFO.
0: Enable interrupt when TX FIFO is empty.
TX FIFO.
0: Enable interrupt when a location is available in
TX FIFO.
SPI Master status register.
1: RX FIFO full.
0: RX FIFO can accept more data from SPI.
Cleared when the cause is removed.
1: Data available in RX FIFO.
0: No data in RX FIFO.
Cleared when the cause is removed.
Interrupt source.
1: TX FIFO empty.
0: Data in TX FIFO.
Cleared when the cause is removed.
Interrupt source.
1: Location available in TX FIFO.
0: TX FIFO full.
Cleared when the cause is removed.
Accesses TX (write) and RX (read) FIFO buffers,
both two bytes deep.
Description