nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 74

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
6.3.1.2
During the boot sequence the content of the flash InfoPage (IP) is transferred to the memory configuration
SFR’s. The same memory configuration SFR’s are used for later interfacing from both SPI and MCU.
Revision 1.1
Address
(hex)
0xF8
Mnemonic
FSR
ENDEBUG
STP
WEN
RDYN
INFEN
RDISMB
Memory configuration SFR
-
Bit
7
6
5
4
3
2
1
0, until cal-
MSB flash
read from
read from
InfoPage
Flash IP
from 16
in NVM
culated
Reset
0, until
1, until
value
flash
0
1
0
1
access
R/W
R/W
SPI
R/W
R/W
R
R
R
74 of 191
a
a
access
SFR
R/W Initial value read from byte ENDEBUG in
R/W Flash write enable latch.
R/W Flash IP Enable
R
R
R
R
Flash Status Register
flash IP.
ENDEBUG:
0: HW debug features disabled
1: HW debug features enabled
When RDISMB=0, ENDEBUG may by set
directly by SFR write, but it can not be
cleared by SFR.
Enable code execution start from protected
flash area (page address NUPP 6:0)
STP:
0: Even number of logic 1 in 16 MSB of NVM
1: Odd number of logic 1 in 16 MSB of NVM
Enables flash write/erase operations from
external interfaces (SPI and HW debug)
WEN will be cleared after each SPI write or
erase operation, but not after a MCU opera-
tions.
Flash ready flag, active low.
Will be set when read out of flash IP is com-
pleted in the MCU boot sequence
Will re-direct general SPI read/write/erase
commands from the flash MB to the IP.
Except SPI command ERASE ALL, which
will erase both MB and IP
Flash MB readback protection enabled,
active low.
RDISMB:
0: External interfaces have full access to the
flash
1: MB read/write/erase and IP erase/write
commands from external interfaces (SPI
and HW debug) disabled.
Will only be reset after use of SPI command
ERASE ALL
Reserved
Description