nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 53

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
Revision 1.1
Address
(Hex)
N/A
1C
1D
a. Please take care when setting this parameter. If the ACK payload is more than 15 byte in 2Mbps mode the
b. This is the time the PTX is waiting for an ACK packet before a retransmit is made. The PTX is in RX mode
c. The
d. If ACK packet payload is activated, ACK packets have dynamic payload lengths and the Dynamic Payload
ARD must be 500µS or more, if the ACK payload is more than 5byte in 1Mbps mode the ARD must be
500µS or more. In 250kbps mode (even when the payload is not in ACK) the ARD must be 500µS or
more.
for a minimum of 250µS, but it stays in RX mode to the end of the packet if that is longer than 250µS.
Then it goes to standby-I mode for the rest of the specified ARD. After the ARD it goes to TX mode and
then retransmits the packet.
should be: 1) read payload through SPI, 2) clear
are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat from step 1).
Length feature should be enabled for pipe 0 on the PTX and PRX. This is to ensure that they receive the
ACK packets with payloads. If the ACK payload is more than 15 byte in 2Mbps mode the ARD must be
500µS or more, and if the ACK payload is more than 5 byte in 1Mbps mode the ARD must be 500µS or
more. In 250kbps mode (even when the payload is not in ACK) the ARD must be 500µS or more.
RX_DR
EN_ACK_PAY
EN_DYN_ACK
Mnemonic
Reserved
FEATURE
Reserved
RX_PLD
DPL_P5
DPL_P4
DPL_P3
DPL_P2
DPL_P1
DPL_P0
EN_DPL
DYNPD
IRQ is asserted by a new packet arrival event. The procedure for handling this interrupt
d
255:0
Bit
7:6
7:3
5
4
3
2
1
0
2
1
0
Table 11. Register map of the RF Transceiver
Reset
Value
X
0
0
0
0
0
0
0
0
0
0
0
Type
53 of 191
R/W Only ‘00’ allowed
R/W Enable dynamic payload length data pipe 5.
R/W Enable dynamic payload length data pipe 4.
R/W Enable dynamic payload length data pipe 3.
R/W Enable dynamic payload length data pipe 2.
R/W Enable dynamic payload length data pipe 1.
R/W Enable dynamic payload length data pipe 0.
R/W Feature Register
R/W Only ‘00000’ allowed
R/W Enables Dynamic Payload Length
R/W Enables Payload with ACK
R/W Enables the W_TX_PAYLOAD_NOACK command
R
RX_DR
Read by separate SPI command.
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO with three
levels.
All RX channels share the same FIFO.
Enable dynamic payload length
(Requires EN_DPL and ENAA_P5)
(Requires EN_DPL and ENAA_P4)
(Requires EN_DPL and ENAA_P3)
(Requires EN_DPL and ENAA_P2)
(Requires EN_DPL and ENAA_P1)
(Requires EN_DPL and ENAA_P0)
IRQ, 3) read
FIFO_STATUS
Description
to check if there