nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 86

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
8.3
8.3.1
In timer mode, Timer 0/1 is incremented every 12 clock cycles.
In the counter mode, the Timer 0/1 is incremented when the falling edge is detected at the corresponding
input pin T0 for Timer 0, or T1 for Timer 1.
Since it takes two clock cycles to recognize a 1-to-0 event, the maximum input count rate is ½ of the oscil-
lator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1
state, an input should be stable for at least 1 clock cycle.
Timer 0 and Timer 1 status and control are in TCON and TMOD register. The actual 16-bit Timer 0 value is in
TH0 (8 msb) and TL0 (8 lsb), while Timer 1 uses TH1 and TL1.
Four operating modes can be selected for Timer 0/1. Two Special Function Registers, TMOD and TCON,
are used to select the appropriate mode.
8.3.1.1
In mode 0, Timer 0/1 is configured as a 13-bit register (TL0/TL1 = 5 bits, TH0/TH1 = 8 bits). The upper
three bits of TL0/TL1 are unchanged and should be ignored.
In mode 1 Timer 0/1 is configured as a 16-bit register.
Revision 1.1
Note: Timer input pins T0, T1 and, T2 must be configured as described in
Functional description
Timer 0 and Timer 1
INTi
GATE
Mode 0 and Mode 1
Fosc
TRi
Ti
/12
Figure 39. Timer 0 and Timer 1 in mode 0 and 1
C/T=0
C/T=1
86 of 191
TLi
THi
section 8.4 on page
TFi
89.