nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 143

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
18.3
18.3.1
The following registers control the SPI master:
Revision 1.1
Address
(Hex)
0xFC
0xFD
Name/mnemonic
maskIrqRxFifoFull
Functional description
spiMasterConfig1
SPI master
spiMasterEnable
clockFrequency
maskIrqRxDa-
maskIrqTxFi-
clockPolarity
SPIMCON0
SPIMCON1
clockPhase
dataOrder
taReady
foEmpty
Bit
6:0
6:4
3:0
3
2
1
0
3
2
1
Reset
value
0x02
0x0F
010
0
0
0
0
1
1
1
143 of 191
Type
R/W SPI Master configuration register 0.
R/W Frequency on MSCK. ( f
R/W Data order (bit wise per byte) on serial output and
R/W Defines the SPI Master’s operating mode together
R/W Defines the SPI Master’s operating mode together
R/W 1: SPI Master is enabled. The clock to the SPI
R/W SPI Master configuration register 1.
R/W 1: Disable interrupt when RX FIFO is full.
R/W 1: Disable interrupt when data is available in RX
R/W 1: Disable interrupt when TX FIFO is empty.
quency.)
input (MMOSI and MMISO respectively).
1: LSBit first, MSBit last.
0: MSBit first, LSBit last.
with SPIMCON0.1, see chapter 18.3.3 SPI timing.
1: MSCK is active ‘low’.
0: MSCK is active ‘high’.
with SPIMCON0.2, see chapter 18.3.3 SPI timing.
1: Sample on trailing edge of MSCK, shift on lead-
ing edge.
0: Sample on leading edge of MSCK, shift on trail-
ing edge.
Master core functionality is running. An SPI trans-
fer can be initiated by the MCU via the 8051 SFR
Bus (TX).
0: SPI Master is disabled. The clock to the SPI
Master core functionality stands still.
0: Enable interrupt when RX FIFO is full.
FIFO.
0: Enable interrupt when data is available in RX
FIFO.
0: Enable interrupt when TX FIFO is empty.
011: 1/16
100: 1/32
101: 1/64
110: 1/64
111: 1/64
000: 1/2
001: 1/4
010: 1/8
Description
ckCpu
is the MCU clock fre-
· f
· f
· f
· f
· f
· f
· f
· f
ckCpu
ckCpu
ckCpu
ckCpu
ckCpu
ckCpu
ckCpu
ckCpu