hm5216165 Elpida Memory, Inc., hm5216165 Datasheet - Page 7

• Manufacturer Part Number: hm5216165
• Description: 16 M Lvttl Interface Sdram 512-kword ? 16-bit ? 2-bank
• Manufacturer: Elpida Memory, Inc.

Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A11) become the
burst write start address. When the single write mode is selected, data is only written to the location specified
by the column address (AY0 to AY7) and the bank select address (A11).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page
(256), this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A11
(BS) and determines the row address (AX0 to AX10). When A11 is Low, bank 0 is activated. When A11 is
High, bank 1 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A11. If
A11 is Low, bank 0 is selected. If A11 is High, bank 1 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
DQM Truth Table
Function
Upper byte write enable/output enable
Lower byte write enable/output enable
Upper byte write inhibit/output disable
Lower byte write inhibit/output disable
Note: H: V
The HM5216165 series can mask input/output data by means of DQMU and DQML. DQMU masks the
upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting
DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the
output buffer becomes High-Z, disabling data output.
DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not
written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details,
refer to the DQM control section of the HM5216165 operating instructions.
I
DOD
is needed.
IH
. L: V
IL
. : V
IH
or V
IL
.
Data Sheet E0167H10
Symbol
ENBU
ENBL
MASKU
MASKL
During writing, data is written by setting
CKE
n - 1
H
H
H
H
n
HM5216165 Series
DQMU
L
H
DQML
L
H
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