hm5216165 Elpida Memory, Inc., hm5216165 Datasheet
hm5216165
Available stocks
Related parts for hm5216165
hm5216165 Summary of contents
Page 1
... HM5216165 Series 16 M LVTTL Interface SDRAM (512-kword Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance. Features 3.3 V Power supply Clock frequency: 100 MHz/83 MHz LVTTL interface Single pulsed RAS ...
Page 2
... HM5216165 Series Ordering Information Type No. HM5216165TT-10H HM5216165TT-12 Pin Arrangement V I/O0 I/ I/O2 I/ I/O4 I/ I/O6 I/ DQML WE CAS RAS A11 A10 V Data Sheet E0167H10 2 Frequency Package 100 MHz 400-mil 50-pin plastic TSOP II (TTP-50D) 83 MHz HM5216165TT Series I/O15 3 48 I/O14 ...
Page 3
... CLK CKE Data Sheet E0167H10 HM5216165 Series Function Address input Row address A0 to A10 Column address Bank select address A11 Data-input/output Chip select Row address strobe command Column address strobe command Write enable command Upper byte input/output mask ...
Page 4
... HM5216165 Series Block Diagram Column address counter Row decoder Memory array Bank 0 2048 row X 256 column X 16 bit Input Output buffer buffer I/O0 – I/O15 Data Sheet E0167H10 4 A0 – A11 A0 – A7 Column address buffer 2048 row X 256 column X 16 bit timing generator A0 – ...
Page 5
... But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is precharged. A11 (input pin): A11 is a bank select signal (BS). The memory array of the HM5216165 is divided into bank 0 and bank 1, both which contain 2048 row and if A11 is High, bank 1 is selected. ...
Page 6
... HM5216165 Series Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Function Ignore command No operation Burst stop in full page Column address and read command Read with auto-precharge Column address and write command Write with auto-precharge Row address strobe and bank act ...
Page 7
... DOD The HM5216165 series can mask input/output data by means of DQMU and DQML. DQMU masks the upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output ...
Page 8
... HM5216165 Series CKE Truth Table Current state Function Active Clock suspend mode entry Any Clock suspend Clock suspend Clock suspend mode exit Idle Auto refresh command Idle Self refresh entry Idle Power down entry Self-refresh Self refresh exit Power down Power down exit Note ...
Page 9
... H BA, CA, A10 READ/READ A L BA, CA, A10 WRIT/WRIT A H BA, RA ACTV L BA, A10 PRE, PALL H REF, SELF L MODE MRS HM5216165 Series Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL ILLEGAL ILLEGAL NOP ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL ILLEGAL ...
Page 10
... HM5216165 Series CS RAS CAS WE Current state Row active Read Read with H auto-precharge ...
Page 11
... L BA, A10 PRE, PALL H REF, SELF L MODE MRS . IL HM5216165 Series Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and new read Term burst and new write Other bank active 3 ILLEGAL on same bank* Term burst write and ...
Page 12
... HM5216165 Series From [PRECHARGE] To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after t has elapsed from the completion of precharge. RP From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. ...
Page 13
... To [ACTV]: This command makes the other bank active. (However, an interval of t Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an auto-refresh cycle (after t enters the IDLE state. Data Sheet E0167H10 HM5216165 Series is required.) RRD is required.) RRD is required.) ...
Page 14
... HM5216165 Series Simplified State Diagram MODE REGISTER (on full page) Write CKE_ WRITE SUSPEND CKE WRITE WITH AP CKE_ WRITEA SUSPEND CKE POWER POWER APPLIED ON Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state ...
Page 15
... Burst read and SINGLE WRITE Data Sheet E0167H10 LMODE Burst Type Sequential Interleave HM5216165 Series A0 Burst Length BT=0 BT ...
Page 16
... HM5216165 Series Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequence Burst length = 8 Starting Ad. Addressing(decimal Sequence ...
Page 17
... Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency-1) cycle after read command set. HM5216165 series can perform a burst read operation. The burst length can be set full-page (256). The start address for a burst read is specified by the column address (AY0 to AY7) and the bank select address (A11) at the read command set cycle ...
Page 18
... HM5216165 Series Burst Length CLK t RCD Command ACTV READ Address Row Column out out 0 out out 0 out 1 out 2 out 3 Dout out 0 out 1 out 2 out out 0 out 1 out 2 out full page (256) Write operation: Burst write or single write mode is selected by the OPCODE (A11, A10, A9, A8) of the mode register ...
Page 19
... AY7) and the bank select address (A11) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0). CLK Command Active Row Address Din Data Sheet E0167H10 t RCD Write Column in 0 CAS latency = Burst length = full page HM5216165 Series 19 ...
Page 20
... HM5216165 Series Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined required before execution of the next command ...
Page 21
... BST command is valid only during full-page burst mode, and is invalid with burst lengths and 8. CAS latency BST to valid data Data Sheet E0167H10 is required between the final valid data input and input of APW in3 l APW ACTV BST to high impedance HM5216165 Series ACTV 21 ...
Page 22
... HM5216165 Series CAS Latency = 1, Burst Length = full page CLK Command I/O (output) out out CAS Latency = 2, Burst Length = full page CLK Command I/O (output) out out CAS Latency = 3, Burst Length = full page CLK Command I/O (output) out out Data Sheet E0167H10 22 BST out out ...
Page 23
... In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths and 8. And an interval of t command. Burst Length = full page CLK Command I/O (input) in Data Sheet E0167H10 is required between the BST command and the next precharge DPL BST PRE/PALL in t DPL cycle BSW HM5216165 Series 23 ...
Page 24
... HM5216165 Series Command Intervals Read command to Read command interval: Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid ...
Page 25
... Column A Row 1 Row 0 (A0-A10) BS (A11) Din in A0 Bank0 Bank1 Bank0 Active Active Write Data Sheet E0167H10 WRIT Column Bank1 Write HM5216165 Series Burst Write Mode Burst Length = 4 Bank0 Burst Write Mode Burst Length = 4 25 ...
Page 26
... HM5216165 Series Read command to Write command interval: Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input ...
Page 27
... READ out B0 out B1 out B2 CAS Latency Column=B Column=B Read Dout READ in A1 out B0 out B1 CAS Latency Column=B Column=B Read Dout HM5216165 Series out B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0 out B2 out B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0 27 ...
Page 28
... HM5216165 Series Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by l possibility that burst read data output will be interrupted, if the precharge command is input during burst read ...
Page 29
... PRE/PALL Dout out A0 CAS Latency = 2, Burst Length = CLK READ PRE/PALL Command Dout CAS Latency = 3, Burst Length = CLK READ PRE/PALL Command Dout Data Sheet E0167H10 High HZP High-Z out HZP High-Z out HZP HM5216165 Series 29 ...
Page 30
... HM5216165 Series Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. WRITE to PRECHARGE Command Interval (same bank): However, if the burst write operation is ...
Page 31
... Bank active to bank active for same bank CLK ACTV Command Address ROW (A0-A10) BS (A11) Bank 0 Active Bank active to bank active for different bank CLK ACTV Command Address ROW:0 (A0-A10) BS (A11) Bank 0 Active Data Sheet E0167H10 HM5216165 Series t RC ACTV ROW:1 t RRD Bank 1 Active . RC ACTV ROW Bank 0 Active 31 ...
Page 32
... HM5216165 Series Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than t CLK Command MRS Address CODE (A0-A11) Mode Register Set Data Sheet E0167H10 32 . RSA ACTV BS & ROW t RSA Bank ...
Page 33
... In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMU/DQML during writing is 0. CLK DQMU /DQML I/O (input) Data Sheet E0167H10 High-Z out 0 out Latency DOD Latency DID HM5216165 Series out ...
Page 34
... HM5216165 Series Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms ...
Page 35
... Value V –1 –1.0 to +4.6 CC Iout 50 P 1.0 T Topr 0 to +70 Tstg –55 to +125 Symbol Min Max 3.0 3 2.0 4 –0.3 0 HM5216165 Series Unit Note °C °C Unit Notes ...
Page 36
... HM5216165 Series DC Characteristics ( 70°C, V Parameter Symbol Operating current I CC1 Standby current I CC2 (Bank Disable) Active standby current I CC3 (Bank active) Burst operating current (CAS latency = 1) I CC4 (CAS latency = 2) I CC4 (CAS latency = 3) I CC4 Refresh current I CC5 Self refresh current ...
Page 37
... — — — 3 CES t 2 — 3 CESP t 1 — 1 CEH HM5216165 Series Unit Notes Max Unit Notes — — — — — ...
Page 38
... HM5216165 Series AC Characteristics ( 70°C, V Parameter Command (CS, RAS, CAS, WE, DQM) setup time Command (CS, RAS, CAS, WE, DQM) hold time Ref/Active to Ref/Active command period Active to precharge command period Active to precharge on full page mode Active command to column command (same bank) Precharge to active command period ...
Page 39
... EP I — — 0 — CCD WCD DID DOD CLE HM5216165 Series Notes RAS DPL ...
Page 40
... HM5216165 Series Relationship Between Frequency and Minimum Latency (cont) Parameter Frequency (MHz) t (ns) CK Register set to active command CS to command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = 3) (CAS latency = 2) (CAS latency = 1) Burst stop to output high impedance ...
Page 41
... Bank 0 Precharge HM5216165 Series Burst length = 4 Bank0 Access = ...
Page 42
... HM5216165 Series Write Cycle CKH CKL CLK V IH CKE t RCD RAS CAS A11 A10 Address t CS DQMU /DQML ...
Page 43
... Active Set Data Sheet E0167H10 b’ High-Z t RCD Output mask Bank 1 Read HM5216165 Series b+3 b’+1 b’+2 b’+3 b’ RCD CAS Latency = 3 Burst Length = ...
Page 44
... HM5216165 Series Read Cycle/Write Cycle CLK CKE RAS CAS WE A11(BS) Address R:a C:a R:b DQMU /DQML I/O (output) I/O (input) Bank 0 Bank 0 Bank 1 Active Read Active V CKE IH CS RAS CAS WE A11(BS) Address R:a C:a R:b DQMU /DQML I/O (output) a a+1 a+2 a+3 I/O (input) Bank 0 Bank 0 Bank 1 Active Write Active ...
Page 45
... R:b C:a' C a+1 a+2 a+3 Bank 1 Bank 0 Bank 0 Active Write Read R:b C:a C a+1 a+3 Bank 0 Bank 0 Bank 1 Write Write Active HM5216165 Series a+1 a+2 a+3 Bank 0 Bank 1 Precharge Precharge C:c c Bank 0 Bank 0 Write Precharge Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst Length = ...
Page 46
... HM5216165 Series Read/Burst Write Cycle CLK V CKE IH CS RAS CAS WE A11(BS) R:a C:a Address DQMU /DQML I/O (input) I/O (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE A11(BS) R:a C:a Address DQMU /DQML I/O (input) I/O (output) Bank 0 Bank 0 Active Read Data Sheet E0167H10 ...
Page 47
... High-Z Burst stop High-Z a+4 a+5 a+6 a+1 a+2 a+3 a+4 a+5 Burst stop HM5216165 Series Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = a+4 a+5 Bank 1 Precharge Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = Bank 1 ...
Page 48
... HM5216165 Series Auto Refresh Cycle CLK CKE RAS CAS WE A11(BS) Address A10=1 DQMU /DQML I/O(input) I/O(output Auto Refresh Precharge If needed Self Refresh Cycle CLK CKE CKE Low CS RAS CAS WE A11(BS) Address A10=1 DQMU /DQML I/O(imput) I/O(output ...
Page 49
... Read Precharge C:a R:b C:b High-Z a a+1 a+2 a+3 b b+1 b+2 b+3 Bank0 Bank1 Write suspend Write suspend Bank1 Precharge Active start end Write HM5216165 Series Read cycle RAS-CAS delay=2 CAS latency=2 Burst length b+1 b+2 b+3 Earliest Bank1 Precharge Write cycle RAS-CAS delay=2 CAS latency=2 ...
Page 50
... HM5216165 Series Power Down Mode CLK CKE CS RAS CAS WE A11(BS) Address A10=1 DQMU /DQML I/O(input) I/O(output Precharge command If needed Power Up Sequence CLK V CKE IH CS RAS CAS WE Valld Address DQMU V IH /DQML I All banks Auto Refresh Precharge Data Sheet E0167H10 ...
Page 51
... Package Dimensions HM5216165TT Series (TTP-50D) 20.95 21.35 Max 50 1 0.80 0.27 0.07 0.13 M 0.25 0.05 1.15 Max 0.10 Dimension including the plating thickness Base material dimension Data Sheet E0167H10 26 25 11.76 0.20 0 – 5 Hitachi Code JEDEC EIAJ Weight (reference value) HM5216165 Series Unit: mm 0.80 0.50 0.10 TTP-50D — — 0. ...
Page 52
... HM5216165 Series Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...