hm5216165 Elpida Memory, Inc., hm5216165 Datasheet - Page 33

• Manufacturer Part Number: hm5216165
• Description: 16 M Lvttl Interface Sdram 512-kword ? 16-bit ? 2-bank
• Manufacturer: Elpida Memory, Inc.

DQM Control
The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of
DQMU/DQML is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting
DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML
to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal
reading operations continue. The latency of DQMU/DQML during reading is 2.
Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be
written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the
previous data is held. The latency of DQMU/DQML during writing is 0.
I/O (output)
I/O (input)
DQMU
/DQML
DQMU
/DQML
CLK
CLK
Data Sheet E0167H10
in 0
out 0
l
DOD
= 2 Latency
in 1
out 1
l
DID
High-Z
= 0 Latency
out 3
HM5216165 Series
in 3
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