hm5216165 Elpida Memory, Inc., hm5216165 Datasheet - Page 17

• Manufacturer Part Number: hm5216165
• Description: 16 M Lvttl Interface Sdram 512-kword ? 16-bit ? 2-bank
• Manufacturer: Elpida Memory, Inc.

Operation of HM5216165 Series
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the
status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank
active command cycle. An interval of t
following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CAS Latency-1) cycle after read command set. HM5216165 series can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page (256). The start address for a burst read is specified by
the column address (AY0 to AY7) and the bank select address (A11) at the read command set cycle. In a read
operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can
be set to 1, 2, 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the
next cycle after the successive burst-length data has been output. When the burst length is full-page (256),
data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be
specified at the mode register.
CAS Latency
Command
Address
Dout
CLK
CL = 1
CL = 2
CL = 3
ACTV
Row
t
RCD
Column
READ
Data Sheet E0167H10
RCD
out 0
is required between the bank active command input and the
out 0
out 1
out 2
out 1
out 0
out 2
out 3
out 1
out 3
out 2
out 3
HM5216165 Series
CL: CAS latency
Burst length = 4
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