hm5216165 Elpida Memory, Inc., hm5216165 Datasheet - Page 26

• Manufacturer Part Number: hm5216165
• Description: 16 M Lvttl Interface Sdram 512-kword ? 16-bit ? 2-bank
• Manufacturer: Elpida Memory, Inc.

HM5216165 Series
Read command to Write command interval:
Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less
than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before
data input.
READ to WRITE Command Interval (1)
READ to WRITE Command Interval (2)
Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. However, DQMU/DQML must be set
High so that the output buffer becomes High-Z before data input.
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DQMU
/DQML
Command
Dout
Din
CLK
Dout
CL=3
CL=1
CL=2
Command
DQMU
/DQML
CL=3
CL=2
CLK
CL=1
Din
Data Sheet E0167H10
READ
READ WRIT
High-Z
in B0
in B1
in B2
2 clock
in B3
WRIT
High-Z
High-Z
High-Z
Burst Length = 4
Burst write