hm5216165 Elpida Memory, Inc., hm5216165 Datasheet - Page 12

• Manufacturer Part Number: hm5216165
• Description: 16 M Lvttl Interface Sdram 512-kword ? 16-bit ? 2-bank
• Manufacturer: Elpida Memory, Inc.

HM5216165 Series
From [PRECHARGE]
To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM enters the
IDLE state after t
has elapsed from the completion of precharge.
RP
From [IDLE]
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto refresh or self refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
From [ROW ACTIVE]
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of t
is required.)
RCD
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t
is required.)
RCD
To [ACTV]: This command makes the other bank active. (However, an interval of t
is required.)
RRD
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval
of t
is required.)
RAS
From [READ]
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of t
is required.)
RRD
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode.
Data Sheet E0167H10
12