hm5216165 Elpida Memory, Inc., hm5216165 Datasheet - Page 15

• Manufacturer Part Number: hm5216165
• Description: 16 M Lvttl Interface Sdram 512-kword ? 16-bit ? 2-bank
• Manufacturer: Elpida Memory, Inc.

Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A11, A10, A9, A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the
column address specified in the write cycle.
Burst read and SINGLE WRITE: Data is only written to the column address specified during the write
cycle, regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle.
A6, A5, A4: (LMODE): These pins specify the CAS latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only “sequential” can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
A11
A11
X
X
X
0
A10
X
X
X
A10
0
OPCODE
A9
0
1
1
0
A9
A8
1
0
1
0
A8
Burst read and SINGLE WRITE
Burst read and burst write
Write mode
A6 A5 A4 CAS Latency
0
0
0
0
1
A7
0
R
R
0
0
1
1
X
Data Sheet E0167H10
A6
0
1
0
1
X
LMODE
A5
R
1
2
3
R
A4
A3
BT
A3
1
0 Sequential
Burst Type
Interleave
A2
BL
A1
A0
A2 A1 A0
F.P. =Full Page (256)
R is Reserved(inhibit)
X: 0 or 1
0
0
0
0
1
1
1
1
HM5216165 Series
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BT=0 BT=1
Burst Length
F.P.
1
2
4
8
R
R
R
1
2
4
8
R
R
R
R
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