k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 51

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
RSL - Transmit Timing
Figure 55 is a timing diagram which shows the detailed
requirements for the RSL output signals on the Channel.
The DQA and DQB signals are outputs to transmit informa-
tion that is received by a Direct RAC on the Channel. Each
signal is driven twice per t
and end of the even transmit window is at the 75% point of
the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the
CTMN
CTM
DQA
DQB
CYCLE
V
X-
0.75•t
interval. The beginning
t
QR
Figure 55: RSL Timing - Data Signals for Transmit
CYCLE
t
QF
t
Q,MAX
Page 49
25% point and at the 75% point of the current cycle. These
transmit points are measured relative to the crossing points
of the falling CTM clock edge. The size of the actual
transmit window is less than the ideal t
by the non-zero values of t
eters are measured at the 50% voltage point of the output
transition.
The t
at the 20% and 80% points of the output transition.
even
QR
0.25•t
and t
CYCLE
QF
t
Q,MIN
rise- and fall-time parameters are measured
V
V
CM
X+
t
Q,MAX
0.75•t
Q,MIN
CYCLE
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
and t
odd
Q,MAX
CYCLE
t
Q,MIN
. The t
/2, as indicated
Q
param-
V
80%
50%
20%
V
80%
50%
20%
V
V
CIH
CIL
QH
QL
™