k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 27

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
The second bubble type t
command) by the controller between a WR and RD
command on the COL pins when there is a WR-WR-RD
sequence to the same device. This bubble enables write data
to be retired from the write buffer without being lost, and is
Control Register Transactions
The RDRAM has two CMOS input pins SCK and CMD and
two CMOS input/output pins SIO0 and SIO1. These provide
CTM/CFM
COL4
DQA8..0
DQB8..0
ROW2
CTM/CFM
COL4
DQA8..0
DQB8..0
ROW2
..COL0
..ROW0
..COL0
..ROW0
t
DBUB1
D (y2)
T
0
T
0
T
1
T
t
RD z1
1
T
CBUB2
RD z1
Q (x2)
2
T
ACT a0
2
T
ACT a0
3
T
3
Transaction y: WR
Transaction b: WR
Transaction z: RD
Transaction a: RD
Transaction c: WR
Transaction d: RD
Transaction e: RD
Transaction f: WR
T
Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length
Figure 21: Interleaved Read Transaction with Two Dualoct Data Length
Transaction y: RD
Transaction b: RD
Transaction d: RD
4
T
Transaction z: RD
Transaction a: RD
Transaction c: RD
Transaction e: RD
Transaction f: RD
CBUB2
4
T
5
T
5
PREX y3
RD z2
T
RD z2
Q (y1)
6
T
6
T
t
7
T
DBUB2
is inserted (as a NOCOP
7
T
8
T
t
8
T
RCD
9
T
RD a1
9
T
RD a1
Q (y2)
10
T
10
ACT b0
T
11
T
11
T
12
T
ACT b0
b0 = {Da,Ba+2,Rb}
d0 = {Da,Ba+6,Rd}
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
12
c0 = {Da,Ba+4,Rc}
f0 = {Da,Ba+2,Rf}
T
t
y0 = {Da,Ba+4,Ry}
b0 = {Da,Ba+2,Rb}
d0 = {Da,Ba+6,Rd}
z0 = {Da,Ba+6,Rz}
13
RBUB1
a0 = {Da,Ba,Ra}
e0 = {Da,Ba,Re}
c0 = {Da,Ba+4,Rc}
f0 = {Da,Ba+2,Rf}
PREX z3
T
13
a0 = {Da,Ba,Ra}
e0 = {Da,Ba,Re}
RD a2
PREX z3
Q (z1)
T
RD a2
14
Q (z1)
T
14
T
15
T
15
T
t
T
16
CAC
16
T
17
T
17
Q (z2)
T
RD b1
Q (z2)
18
T
18
T
ACT c0
MSK (y2)
19
T
WR b1
t
19
Page 25
T
CBUB1
20
T
ACT c0
20
T
21
T
b1 = {Da,Ba+2,Cb1}
d1 = {Da,Ba+6,Cd1}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
c1 = {Da,Ba+4,Cc1}
f1 = {Da,Ba+2,Cf1}
Q (a1)
21
PREX a3
b1 = {Da,Ba+2,Cb1}
d1 = {Da,Ba+6,Cd1}
T
y1 = {Da,Ba+4,Cy1}
t
z1 = {Da,Ba+6,Cz1}
c1 = {Da,Ba+4,Cc1}
a1 = {Da,Ba,Ca1}
e1 = {Da,Ba,Ce1}
f1 = {Da,Ba+2,Cf1}
RD b2
Q (a1)
22
RC
explained in detail in Figure 18. There would be no bubble if
address c0 and address d0 were directed to different devices.
This bubble appears on the DQA and DQB pins as t
between a write data dualoct D and read data dualoct Q. This
bubble also appears on the ROW pins as t
serial access to a set of control registers in the RDRAM.
These control registers provide configuration information to
the controller during the initialization process. They also
T
a1 = {Da,Ba,Ca1}
e1 = {Da,Ba,Ce1}
22
T
23
WRA b2
PREX a3
T
23
T
24
T
24
T
25
T
25
Q (a2)
T
RD c1
Q (a2)
26
T
26
T
ACT d0
MSK (b1)
27
T
WR c1
27
T
28
T
28
T
29
T
29
D (b1)
PREX b3
T
t
Q (b1)
30
RD c2
T
b2= {Da,Ba+2,Cb2}
d2= {Da,Ba+6,Cd2}
RBUB2
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
30
c2= {Da,Ba+4,Cc2}
f2= {Da,Ba+2,Cf2}
T
y2= {Da,Ba+4,Cy2}
b2= {Da,Ba+2,Cb2}
d2= {Da,Ba+6,Cd2}
z2= {Da,Ba+6,Cz2}
MSK (b2)
a2= {Da,Ba,Ca2}
e2= {Da,Ba,Ce2}
c2= {Da,Ba+4,Cc2}
f2= {Da,Ba+2,Cf2}
31
T
WRA c2
a2= {Da,Ba,Ca2}
e2= {Da,Ba,Ce2}
31
T
32
T
t
32
T
RR
33
T
33
D (b2)
T
RD d1
Q (b2)
34
T
34
T
ACT e0
MSK (c1)
35
NOCOP
T
35
Preliminary
T
Direct RDRAM
Rev. 0.9 Jan. 2000
T
36
ACT d0
36
T
t
37
T
CBUB2
same bank as transaction a
37
D (c1)
PREX c3
T
Transaction e can use the
RDd2
Q (c1)
38
T
same bank as transaction a
Transaction e can use the
38
T
MSK (c2)
39
NOCOP
T
39
T
40
y3 = {Da,Ba+4}
b3 = {Da,Ba+2}
d3 = {Da,Ba+6}
T
z3 = {Da,Ba+6}
c3 = {Da,Ba+4}
f3 = {Da,Ba+2}
40
y3 = {Da,Ba+4}
b3 = {Da,Ba+2}
d3 = {Da,Ba+6}
t
z3 = {Da,Ba+6}
c3 = {Da,Ba+4}
T
a3 = {Da,Ba}
e3 = {Da,Ba}
f3 = {Da,Ba+2}
RBUB2
DBUB1
41
T
a3 = {Da,Ba}
e3 = {Da,Ba}
D (c2)
41
T
ACT f0
RD e1
Q (c2)
42
T
42
T
43
T
ACT e0
RDd0
43
.
T
44
T
44
T
45
T
DBUB2
45
PREX d3
T
RD e2
Q (d1)
46
T
46
T
47
T
47
RDf1
™