k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 28

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
allow an application to select the appropriate operating mode
of the RDRAM.
SCK (serial clock) and CMD (command) are driven by the
controller to all RDRAMs in parallel. SIO0 and SIO1 are
connected (in a daisy chain fashion) from one RDRAM to
SCK
CMD
Write and read transactions are each composed of four
packets, as shown in Figure 23 and Figure 24. Each packet
consists of 16 bits, as summarized in Table 14 and Table 15.
The packet bits are sampled on the falling edge of SCK. A
transaction begins with a SRQ (Serial Request) packet. This
packet is framed with a 11110000 pattern on the CMD input
(note that the CMD bits are sampled on both the falling edge
and the rising edge of SCK). The SRQ packet contains the
SOP3..SOP0 (Serial Opcode) field, which selects the trans-
action type. The SDEV5..SDEV0 (Serial Device address)
selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is
set, then all RDRAMs are selected. The SA (Serial Address)
SCK
CMD
SIO0
SIO0
SIO1
SIO1
1111
1111
0000
0000
T
T
4
4
SRQ - SWR command
SRQ - SWR command
SRQ - SRD command
SRQ - SRD command
00000000...00000000
00000000...00000000
First 3 packets are repeated
Each packet is repeated
from SIO0 to SIO1
from SIO0 to SIO1
Figure 23: Serial Write (SWR) Transaction to Control Register
Figure 24: Serial Read (SRD) Transaction Control Register
T
T
20
20
00000000...00000000
00000000...00000000
SA
SA
SA
SA
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T
T
36
36
the next. In normal operation, the data on SIO0 is repeated
on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet).
The controller connects to SIO0 of the first RDRAM.
packet contains a 12 bit address for selecting a control
register.
A write transaction has a SD (Serial Data) packet next. This
contains 16 bits of data that is written into the selected
control register. A SINT (Serial Interval) packet is last,
providing some delay for any side-effects to take place. A
read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the
control register. The SD read data packet travels in the oppo-
site direction (towards the controller) from the other packet
types. The SCK cycle time will accomodate the total delay.
addressed RDRAM drives
00000000...00000000
00000000...00000000
0/SD15..SD0/0 on SIO0
SINT
SINT
SD
SD
T
0
0
T
52
52
0/SD15..SD0/0 from SIO1 to SIO0
non-addressed RDRAMs pass
00000000...00000000
00000000...00000000
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
controller drives
next transaction
SINT
SINT
0 on SIO0
SD
SD
next transaction
T
T
1111
68
68
0
0
1111
™
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0