k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 38

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the t
t
TCLS1..0 - Specifies the t
t
TCDLY0 - Specifies the t
t
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values “011” (3•t
(5•t
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t
equal to the t
offset between a ROW packet (which places a device
at ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values “0111” (7•t
“1010” (10•t
which matches the largest t
4•t
system. Thus, if an RDRAM with t
were present, then TFRM would be programmed to
5•t
15 14 13 12 11 10 9
CYCLE
CYCLE
CYCLE
15 14 13 12 11 10 9
0
0
Control Register: TPARM
Control Register: TFRM
CYCLE
CYCLE
CYCLE
CYCLE
0
0
units. This should be “10” (2•t
units. Should be “10” (2•t
units. This adds a programmable delay to Q
0
0
) that is present in an RDRAM in the memory
.
).
units. This value must be greater than or
0
0
CYCLE
Figure 40: TFRM Register
FRM,MIN
0
0
0
0
). TFRM is usually set to the value
0
0
parameter. This is the minimum
8
0
8
0
CYCLE
CDLY0-C
CLS-C
CAS-C
RCD,MIN
7
0
7
0
6
0
6
0
) through “101”
TCDLY0
core parameter in
core parameter in
CYCLE
CYCLE
RCD,MIN
core parameter in
5
0
5
0
parameter (modulo
Address: 049
CYCLE
4
0
4
0
Address: 048
).
) through
3
3
TCLS
= 9•t
TFRM3..0
Figure 39: TPARM Register
).
2
2
CYCLE
1
1
TCAS
16
0
0
16
Page 36
The equations relating the core parameters to the
datasheet parameters follow:
.
TCDLY0
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t
parameter in t
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values “000” (0•t
“010” (2•t
t
t
t
t
t
t
15 14 13 12 11 10 9
Control Register: TCDLY1
0
CAS-C
CLS-C
CPS-C
OFFP
RCD
CAC
011
011
011
100
101
0
= t
= 3•t
= t
(see table below for programming ranges)
= t
= 1•t
= 4•t
= 2•t
= 2•t
0
3•t
3•t
3•t
4•t
5•t
RCD-C
t
RCD-C
CDLY0-C
CPS-C
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
0
Figure 41: TRDLY Register
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
0
+ 1•t
+ t
). Refer to Figure 39 for more details.
- 1•t
TCDLY1
0
+ t
CAS-C
000
001
010
010
010
CYCLE
CYCLE
CLS-C
units. This adds a programmable
0
Not programmable
+ t
8
0
0 t
1 t
2 t
2 t
2 t
t
Preliminary
CDLY1-C
Direct RDRAM
+ t
Rev. 0.9 Jan. 2000
- t
CLS-C
7
0
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CLS-C
CDLY0-C
6
0
- 1•t
5
0
CYCLE
Address: 04a
CYCLE
4
0
CDLY1-C
+ t
10 t
11 t
12 t
8 t
9 t
t
CDLY1-C
3
0
CAC
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
) through
2
0
TCDLY1
core
1
16
0
™