k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 44

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
Refresh
RDRAMs, like any other DRAM technology, use volatile
storage cells which must be periodically refreshed. This is
accomplished with the REFA command. Figure 50 shows an
example of this.
The REFA command in the transaction is typically a broad-
cast command (DR4T and DR4F are both set in the ROWR
packet), so that in all devices bank number Ba is activated
with row number REFR, where REFR is a control register in
the RDRAM. When the command is broadcast and ATTN is
set, the power state of the RDRAMs (ATTN or STBY) will
remain unchanged. The controller increments the bank
address Ba for the next REFA command. When Ba is equal
to its maximum value, the RDRAM automatically incre-
ments REFR for the next REFA command.
On average, these REFA commands are sent once every
t
address bits and RBIT are the number of row address bits) so
that each row of each bank is refreshed once every t
interval.
The REFA command is equivalent to an ACT command, in
terms of the way that it interacts with other packets (see
Table 10). In the example, an ACT command is sent after
t
REFA command.
A second ACT command can be sent after a time t
address c0, the same bank (or an adjacent bank) as the REFA
command.
Note that a broadcast REFP command is issued a time t
after the initial REFA command in order to precharge the
REF
RR
CTM/CFM
COL4
DQA8..0
DQB8..0
ROW2
..COL0
..ROW0
to address b0, a different (non-adjacent) bank than the
/2
BBIT+RBIT
T
Transaction d: REFA
Transaction a: REFA
0
REFA a0
(where BBIT are the number of bank
Transaction b: xx
Transaction c: xx
T
1
T
2
T
3
T
4
T
5
T
6
T
t
7
RR
Figure 50: REFA/REFP Refresh Transaction Example
T
8
ACT b0
b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}
T
9
d0 = {Broadcast,Ba+1,REFR}
T
a0 = {Broadcast,Ba,REFR}
10
T
11
c0 = {Dc, ==Ba, Rc}
T
12
T
13
T
14
T
15
t
RC
RAS
T
REF
16
to
T
17
RAS
T
18
T
19
Page 42
t
T
RC
20
T
21
refreshed bank in all RDRAMs. After a bank is given a
REFA command, no other core operations (activate or
precharge) should be issued to it until it receives a REFP.
It is also possible to interleave refresh transactions (not
shown). In the figure, the ACT b0 command would be
replaced by a REFA b0 command. The b0 address would be
broadcast to all devices, and would be {Broad-
cast,Ba+2,REFR}. Note that the bank address should skip by
two to avoid adjacent bank interference. A possible bank
incrementing pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10,
12, 14, 0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28,
30, 16, 18, 20, 22, 31}. Every time bank 31 is reached, the
REFA command would automatically increment the REFR
register.
A second refresh mechanism is available for use in PDN and
NAP power states. This mechanism is called self-refresh
mode. When the PDN power state is entered, or when NAP
power state is entered with the NSR control register bit set,
then self-refresh is automatically started for the RDRAM.
Self-refresh uses an internal time base reference in the
RDRAM. This causes an activate and precharge to be
carried out once in every t
REFB and REFR control registers are used to keep track of
the bank and row being refreshed.
Before a controller places an RDRAM into self-refresh
mode, it should perform REFA/REFP refreshes until the
bank address is equal to the maximum value. This ensures
that no rows are skipped. Likewise, when a controller returns
an RDRAM to REFA/REFP refresh, it should start with the
minimum bank address value (zero).
T
22
T
t
23
REF
T
24
REFP a1
a1 = {Broadcast,Ba}
T
25
/2
T
BBIT+RBIT
26
T
27
T
28
T
29
T
30
T
t
31
RP
T
32
ACT c0
T
33
REF
T
34
T
/2
35
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
T
BBIT+RBIT
36
BBIT = # bank address bits
T
RBIT = # row address bits
37
REFR = REFR8..REFR0
REFB = REFB3..REFB0
T
38
T
39
T
40
interval. The
T
41
T
42
T
43
REFA d0
T
44
T
45
T
46
T
47
™