k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 14

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
ROW-to-ROW Packet Interaction
Figure 6 shows two packets on the ROW pins separated by
an interval t
contents. No other ROW packets are sent to banks
{Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless
noted otherwise. Table 10 summarizes the t
for all possible cases.
Case #
RR1
RR2
RR3
RR4
RR5
RR6
RR7
RR8
RR9
RR10
RR10a
RR10b
RR11
RR12
RR13
RR14
RR15
RR16
CTM/CFM
COL4
DQA8..0
ROW2
DQB8..0
Figure 6: ROW-to-ROW Packet Interaction- Timing
..COL0
..ROW0
ROPa
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
PRER
PRER
PRER
PRER
PRER
PRER
PRER
PRER
PRER
PRER
RRDELAY
T
Transaction b: ROPb
Transaction a: ROPa
0
ROPa a0
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
Da
T
1
T
2
T
which depends upon the packet
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
3
T
4
T
5
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
T
6
T
7
T
ROPb
ACT
ACT
ACT
ACT
PRER
PRER
PRER
PRER
ACT
ACT
ACT
ACT
ACT
ACT
PRER
PRER
PRER
PRER
ROPb b0
8
Table 10: ROW-to-ROW Packet Interaction - Rules
T
9
a0 = {Da,Ba,Ra}
b0= {Db,Bb,Rb}
T
10
T
11
Db
/= Da
== Da
== Da
== Da
/= Da
== Da
== Da
== Da
/= Da
== Da
== Da
== Da
== Da
== Da
/= Da
== Da
== Da
== Da
T
12
RRDELAY
T
t
13
RRDELAY
T
14
T
Bb
xxxx
/= {Ba,Ba+1,Ba-1}
== {Ba+1,Ba-1}
== {Ba}
xxxx
/= {Ba,Ba+1,Ba-1}
== { Ba+1,Ba-1}
== {Ba}
xxxx
/= {Ba,Ba 1,Ba 2}
== {Ba+2}
== {Ba-2}
== {Ba+1,Ba-1}
== {Ba}
xxxx
/= {Ba,Ba+1,Ba-1}
== {Ba+1,Ba-1}
== Ba
15
T
16
T
values
17
T
18
T
19
Page 12
T
Cases RR1 through RR4 show two successive ACT
commands. In case RR1, there is no restriction since the
ACT commands are to different devices. In case RR2, the
t
banks. Cases RR3 and RR4 are illegal (as shown) since bank
Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
is inserted, t
and t
Cases RR5 through RR8 show an ACT command followed
by a PRER command. In cases RR5 and RR6, there are no
restrictions since the commands are to different devices or to
non-adjacent banks of the same device. In cases RR7 and
RR8, the t
before it can be precharged.
Cases RR9 through RR12 show a PRER command followed
by an ACT command. In cases RR9 and RR10, there are
essentially no restrictions since the commands are to
different devices or to non-adjacent banks of the same
device. RR10a and RR10b depend upon whether a bracketed
bank (Ba 1) is precharged or activated. In cases RR11 and
RR12, the same and adjacent banks must all wait t
sense amp and bank to precharge before being activated.
RR
restriction applies to the same device with non-adjacent
Rb
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
x..x
RP
to the next ACT).
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RAS
RRDELAY
PACKET
RR
RC
RC
PACKET
PACKET
RAS
RAS
PACKET
PACKET
PACKET
PACKET
RP
RP
PACKET
PP
PP
PP
RRDELAY
- illegal unless PRER to Ba/Ba+1/Ba-1
- illegal unless PRER to Ba/Ba+1/Ba-1
restriction means the activated bank must wait
/t
/t
RP
RP
if Ba+1 is precharged/activated.
if Ba-1 is precharged/activated.
is t
RC
(t
RAS
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
to the PRER command,
RP
Example
Figure 11
Figure 11
Figure 10
Figure 10
Figure 11
Figure 11
Figure 10
Figure 15
Figure 12
Figure 12
Figure 10
Figure 10
Figure 12
Figure 12
Figure 12
Figure 12
for the
™