k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 49

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
RSL - Clocking
Figure 53 is a timing diagram which shows the detailed
requirements for the RSL clock signals on the Channel.
The CTM and CTMN are differential clock inputs used for
transmitting information on the DQA and DQB, outputs.
The CFM and CFMN are differential clock outputs used for
receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points
where they cross. The t
the falling CFM edge to the falling CFM edge. The t
t
to falling edges of CFM. The t
parameters are measured at the 20% and 80% points.
CH
CTMN
CFMN
parameters are measured from falling to rising and rising
CTM
CFM
t
TR
CYCLE
t
CYCLE
t
t
parameter is measured from
CR
CL
V
CYCLE
t
X-
CL
V
and t
X-
CF
rise- and fall-time
Figure 53: RSL Timing - Clock Signals
CL
and
t
CH
Page 47
t
CH
Most timing is measured relative to the points where they
cross. The t
CTM edge to the falling CTM edge. The t
eters are measured from falling to rising and rising to falling
edges of CTM. The t
ters are measured at the 20% and 80% points.
The t
tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
t
CF
t
TR
CF
t
CR
parameter specifies the phase difference that may be
t
CR
CYCLE
parameter is measured from the falling
V
V
CM
CR
X+
V
V
CM
X+
and t
CF
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
rise- and fall-time parame-
t
CR
t
CR
t
CF
t
CF
CL
and t
CH
V
V
80%
50%
20%
V
80%
50%
20%
V
param-
CIH
CIH
CIL
CIL
™