k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 3

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 288Mbit Direct Rambus DRAMs (RDRAM ) are
extremely high-speed CMOS DRAMs organized as 16M
words by 18 bits. The use of Rambus Signaling Level (RSL)
technology permits 600MHz to 800MHz transfer rates while
using conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data trans-
fers at 1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage/band-
width or for error correction.
Features
The 288Mbit Direct RDRAMs are offered in a CSP hori-
zontal package suitable for desktop as well as low-profile
add-in card and mobile applications.
Highest sustained bandwidth per DRAM device
Low latency features
Advanced power management:
Organization: 2Kbyte pages and 32 banks, x 18
Used Rambus Signaling Level (RSL) for up to 800MHz oper-
- 1.6GB/s sustained data transfer rate
- Separate control/data buses for maximum efficiency
- Separate row and column control buses for easy
scheduling and highest performance
- 32 banks: four transactions can take place simul-
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
- Multiple low power states allows flexibility in power
consumption versus time to active state
- Power-down self-refresh
- x18 organization allows ECC configurations or
ation
taneously at full bandwidth data rates
increased storage and bandwidth
Page 1
Key Timing Parameters/Part Numbers
a.The “32s” designation indicates that this RDRAM core is composed of 32
banks which use a “split” bank architecture.
b.The “N” designator indicates the normal package
c.The “C” designator indicates that this RDRAM core uses Normal Power
Self Refresh.
Organization
512Kx18x32s
Figure 1: Direct RDRAM CSP Package
a
-CG6
-CK7
-CK8
Bin
K4R88xx69A-Nxxx
Freq.
Speed
MHz
600
711
800
I/O
SAMSUNG
t
RAC
Time) ns
Access
53.3
Preliminary
45
45
Direct RDRAM
Rev. 0.9 Jan. 2000
(Row
K4R881869M-N
K4R881869M-NCK7
K4R881869M-NCK8
001
Part Number
b
C
c
G6
™