kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet - Page 97

• Manufacturer Part Number: kfm2g16q2m-deb8
• Description: 2gb Muxonenand M-die
• Manufacturer: Samsung Semiconductor, Inc.

A/DQ15
A/DQ0:
3.7.2.3 Programmable Burst Read Latency Operation
MuxOneNAND2G(KFM2G16Q2M-DEBx)
MuxOneNAND4G(KFN4G16Q2M-DEBx)
MuxOneNAND8G(KFK8G16Q2M-DEBx)
Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks.
The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with
the (n+1)th rising edge.
The number of total initial access cycles is programmable from three to seven cycles. After the number of programmed burst clock
cycles is reached, the rising edge of the next clock cycle triggers the next burst data.
Four Clock Burst Read Latency (BRWL=4 case)
3.7.3
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine
when the initial word of burst data is ready to be read.
To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see
Section 2.8.19, "System Configuration1 Register").
The rising edge of RDY which is derived at the same cycle of data fetch clock indicates the initial word of valid burst data.
3.7.4
When the CE or OE input is at V
The outputs are placed in the high impedance state.
*Note: BRWL=4, HF=0 is recommended for 40MHz~66MHz. For frequency over 66MHz, BRWL should be 6 or 7 while HF=1.
RDY
CLK
AVD
OE
CE
Hi-Z
Also, for frequency under 40MHz, BRWL can be reduced to 3, and HF=0.
Handshaking Operation
Output Disable Mode Operation
Address
Valid
-1
See Timing Diagrams 6.1 and 6.2
0
IH
1
, output from the device is disabled.
t
2
IAA
t
RDYA
3
D6
4
t
Rising edge of the clock cycle following last read latency
triggers next burst data
RDYS
97
D7
t
BA
D0
D1
D2
FLASH MEMORY
D3
D7
D0
Hi-Z